1. Multiplexing Level for the PANDA MVD
ZEL and IKP, Forschungszentrum Jülich

2. MVD Readout Concept General PANDA DAQ concept
Specific MVD architecture
GBT:
Serial optical link
3.28 Gb/s
Under development at CERN
MMB
(MVD
Multiplexing
Board)
Detector
Module
Service Board
LVDS
GBT

3. MMB (MVD Multiplexing Module)
Designed as a MicroTCA Module
Directly pluggable into a Compute Node version 3
Scalable architecture supporting test systems and subsystems
MicroTCA backplane for management, control and setup

4. Development of 10 Gb/s link
FPGA: Xilinx XC5VLX30T with FF665 package, well known in ZEL
Avoid 10 GigaBit/s on PCB (8B/10B-Codierung => 12,5 GHz)
Use XAUI interface (4 * 2,5 GBit/s)
Use X2 transceiver Modul FTLX8541E2
Synchronization of Vertex5 MGT-Ports?
USE Parallel-to-XAUI SERDES: PM8358 , well known from QPACE project
In future: Use SFP+ tranceiver

5. First prototype module
PCIe module for easy testing and uplink functinality
Major issue: FPGA code development for DMA
SC-connector
Finisar
FTLX8541E2
XAUI (4 x 3,125 Gbit/s)
PM8358
PCIe (4 Lanes)
XGMII (32 Bit parallel)
XC5VLX30T

6. PCIe board for the 10G optical uplink
Status:
First Protoype available
Hardware tests showed serious problems => redesign is going on