1. Fixed-pointed FFT model
Speaker & Reporter:洪聖揚
Adviser：Prof. An-Weu Wu
Date：2006/12/11

2. Outline Floating point simulation Fixed point model with truncation
SQNR with input, output and twiddle factor
Optimize the choice of bits
Conclusion

3. Simulation Use MATLAB compile BFI、BFII as module For loop as counter
Input： (1)data input
(2)Out of BFI
(3)Register
Output： (1)Output of BFI
(2)Output of BFII
(3)Output as Register
input
Register
N/2
N/4
BF I
BF II
Function： BFI　BFII
Control by for loop s t
Out of BFII
Data input
Out of BFI

4. Result
Use fft function in MATLAB for verification

5. Outline Fixed point model with truncation Floating point simulation
SQNR with input, output and twiddle factor
Optimize the choice of bits
Conclusion

6. Methodology of truncation
Separate total bits into two parts :
integer part and fraction part
Inverse the digits to the decimation ;construct the truncated data
Use the truncated data during the calculation

7. Code for Truncation Truncate data of abs(real(x)) and abs(imag(x))
Recovery the fraction data
Recovery the signed data

8. Truncation Requirements
Dynamic range for input data:[-4 4]
Number of bits for input data:10~14
Number of bits for output data:16~20
Number of bits for twiddle factor: Designer-defined
SQNR>=50dB

9. Definition of input and output
Defined as Input
Defined as Output of previous stage

10. Outline Floating point simulation Fixed point model with truncation
SQNR with input, output and twiddle factor
Optimize the choice of bits
Conclusion

11. Intuition of integer part
The input integer part should increasing 1 bit through the adder
The integer part of twiddle factors can be reduced to 1 bits
Input integer bits reduced to 3 bits ,as the final output integer bits reduced to 9 bits

12. More Integer, Less precision
Output integer and total bit of input fixed, add input integer
Input integer and total output bit fixed, add output integer
Fixed integer output and total bit of input
Fixed integer input and total bit of output

13. Intuition of fraction part
There is much room for fraction bits decision
Just compare output bit and twiddle factor to optimize the minimum bits.
The fraction part dominates the precision of output

14. Tuning twiddle factoer…
Fixed twiddle factor total：13 bit and 14 bit
Use 1 bit to store integer data
At total bits=12
At total bits=14

15. Saturation in twiddle factor
Fixed twiddle factor total：13 bit and 14 bit
Use 1bit to store integer part
At total bits=14
At total bits=13

16. The Effect of input and output fraction
total input bits:12bits，total output bits:18bits
Integer fixed at 3 bit in input,9 bit in output ,1 bit in twiddle
Twiddle factor fraction：8~16 bit
At output total bits=18
At input total bits=12

17. After simulation analysis
When twiddle factor increasing, SQNR is more higher, but saturation at total bit=16
When output fraction bit increasing
- bits of twiddle is small, not obviously change in SQNR
- bits of twiddle is large, SQNR is more higher

18. Outline Floating point simulation Fixed point model with truncation
SQNR with input, output and twiddle factor
Optimize the choice of bits
Conclusion

19. Optimize the Choice of bits
Requirement SQNR over than 50dB
Better reducing bits of output than twiddle
Choose fraction bits of output and input be equal or more
Fixed twiddle factor at maximum to choose output minimum, then reduce twiddle factor.

20. Find possible region of input & output
First, fixed twiddle factor at total bit=13
At total bits=13
Over than 50dB
Possible output min

21. Find possible twiddle factor
Second, fixed output and input at possible minimum region, find out the twiddle factor minimum.
Ex. Fixed output at
8 fraction
twiddle min
Input min
At fraction output=8

22. Choose of Optimal bits Result： Best Solution! Input Output Twiddle
SQNR 10 16 11 17 18 12
Best Solution!

23. Conclusion and future Conclusion：
1.Finished floating and fixed point FFT model
2.Analyzed and optimize the bits for truncate input, output, and twiddle factor
In future：
--RTL code before 12/27
--synthesis as soon as possible…