1. Programmable Logic Devices
Sharif University of Technology
Department of Computer Engineering
Programmable Logic Devices
Alireza Ejlali

2. Advantages of PLDs Field Programmable Erasable and reprogrammable
Reduced TTM
Custom computing
Erasable and reprogrammable
Updating a device or correction of errors.
Reuse the device for a different design.
Ideal for course laboratories.

3. Programmable Logic Technologies
Simple PLDs (SPLD)
Read Only Memory (ROM)
Programmable Array Logic (PAL)
Programmable Logic Array (PLA)
Complex PLDs (CPLD) /Field- Programmable Gate Array (FPGA)

4. ROM, PAL and PLA Configurations
Fixed
Programmable
Programmable
Inputs
AND array
Outputs
Connections
OR array
(decoder)
(a) Programmable read-only memory (PROM)
Programmable
Inputs
Programmable
Fixed
Outputs
Connections
AND array
OR array
(b) Programmable array logic (PAL) device
Programmable
Programmable
Programmable
Programmable
Inputs
Outputs
Connections
AND array
Connections
OR array
(c) Programmable logic array (PLA) device

5. ROM D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 A B C F0 F1 F2 F3 X

6. PAL I C B A X AND gates inputs Product term F 10 11 12 9 1 2 3 4 5 6 79 1 2 3 4 5 6 7 8
AND gates inputs
Product
term 10 11 12 F I C B A X

7. PAL with FFs

8. PLA
Fuse intact
Fuse blown 1 F 2 X A B C 3 4
A B
A C
B C

9. SPLD Structure

10. OTP & RP SPLDs
One time programmable (OTP)
Re-Programmable (RP)

11. Multiple PAL like blocks Reprogrammable Global Interconnects
CPLD
Multiple PAL like blocks
Reprogrammable
Global Interconnects