1. Revision
CHAPTER 6

3. Figure 6.2. Energy band diagram of an ideal MOS diode at V = 0.
THE MOS DIODES (cont.)
Figure Energy band diagram of an ideal MOS diode at V = 0.

5. KEYWORDS :
Work Function, : Energy difference between the Fermi level and the vacuum level.
b) Electron affinity, : Energy difference between the conduction band edge and the vacuum level in the semiconductor.
c) : Energy difference between the Fermi level EF and the intrinsic Fermi level Ei

6. ENERGY BAND DIAGRAMS AND CHARGE DISTRIBUTIONS OF AN IDEAL MOS DIODE
THE MOS DIODES (cont.)
ENERGY BAND DIAGRAMS AND CHARGE DISTRIBUTIONS OF AN IDEAL MOS DIODE
ACCUMULATION CASE :
V<0 is applied to the metal plate, holes will be induced at the SiO2 – Si interface.
Bands near the semiconductor surface are bent upward. It cause an increase in the energy Ei-EF which in turn gives rise to an enhanced concentration and accumulation of holes near the oxide-semiconductor interface
No current flows.
b) DEPLETION CASE :
V>0 is applied, the energy bands near the semiconductor surface are bent downward.
Holes (majority carriers) are depleted.

7. THE MOS DIODES (cont.) c) INVERSION CASE :
Larger positive voltage applied, energy bands bend downward even more so the Ei at the surface crosses over the Fermi level.
The positive gate voltage starts to induce excess electrons at the SiO2 – Si interface.
Electrons greater than holes, thus the surface is inverted.

8. THE MOS DIODES (cont.) The surface depletion region
Figure Energy band diagrams at the surface of a p-type semiconductor.

9. Ideal MOS Curves Vo o QS Co
No work function differences – applied voltage appear partly across oxide & across semiconductor Vo
Potential across the oxide
Field in the oxide
Charge per unit area
Oxide capacitance per unit area o QS Co
(a) Band diagram of an ideal MOS diode. (b) Charge distributions under inversion condition. (c) Electric field distribution. (d) Potential distribution

10. Threshold voltage: C Total capacitance of MOS diode
Co Oxide capacitance
Cj Semiconductor depletion-layer capacitance
W Width of depletion
o Permittivity in vacuum
ox Insulator permittivity
(a) High-frequency MOS C-V curve showing its approximated segments (dashed lines). Inset shows the series connection of the capacitors. (b) Effect of frequency on the C-V curve.2
Minimum value of total capacitance:
Threshold voltage:

11. Metal-SiO2-Si : most extensively studied
The SiO2 – Si MOS diode
Metal-SiO2-Si : most extensively studied
Work function difference qms  0 (for metal electrodes)
Work function semiconductor qs (Energy difference: Between vacuum level – Fermi level)
Work function metal qm  difference: qms (qms - qs)
Aluminum : qm = 4.1eV
Polysilicon : n+ qm = 4.05eV
p+ qm = 5.05eV
Work function difference as a function of background impurity concentration for Al, n+-, and p+ polysilicon gate materials.

12. Interface Traps & Oxide Charges
MOS diode is affected by charges in the oxide & traps in the SiO2-Si interface
Classifications of traps & charges:
Interface-trapped charge
Fixed oxide charge
Oxide trapped charge
Mobile ionic charge
Interface trapped charge Qit
due to SiO2-Si interface properties & chemical composition in the interface
Location: SiO2-Si
Interface trap density (number of interface traps per unit area & per eV)  in 100 the interface trap density is an order of magnitude smaller than 111

13. Fixed charge, Qf
Location: within 3nm of the SiO2-Si interface
The charge is fixed – cannot be charged or discharged
Qf is generally +ve & can be regarded as a charge sheet located at the SiO2-Si interface
Oxide-trapped charges, Qot
Associated with defects in SiO2
The charges can be created (Eg. by X-ray radiation or high energy electron bombardment) – traps are distributed inside the oxide layer.
Can be removed by low temperature annealing
Mobile ionic charges, Qm
Eg. Sodium & alkali ions – mobile under raised-temperature (Eg. >100oC) & high field operations.
Stability problem in semiconductor devices operated under high bias & high temperature conditions
Mobile ion charges move back & forth through the oxide layer  cause shifts of CV curves along voltage axis
Mobile ions have to be eliminated

14. MOSFET

15. MOSFET

16. BASIC OPERATION When VG=0 :
Source and drain electrodes correspond to two p-n junctions connected
back to back. Zero current flow from source to drain ideally. This create
an inversion layer which will be a threshold voltage, Vt prior current flow.
When small positive voltage applied to gate, VG the central MOS structure
is inverted and a channel is formed. Current begin to flow.
2) Low Drain Voltage :
When a small drain voltage applied, electrons will flow from the source to the drain through the conducting channel. The channel acts as a resistor, and the drain current ID proportional to the drain voltage. Current flow can be controlled by using gate voltage. This create a linear region in IV curve

17. 3) Onset On Saturation :
If VD increases, the inversion layer width reduces as the VD is larger than VG. At one point, the inversion layer will disappear as the VD is enough to compensate the inversion layer strength. This point is called pinch off point and the VD saturates.
4) Beyond saturation :
Beyond pinch off point, maximum number of electron will flow from source to drain. Therefore, the current saturation occur. The current flow now controlled by VG and independent of VD. The major changes is the reduction of channel length.

18. For a given VG : ID increases linearly with VD then saturated
Figure Idealized drain characteristics of a MOSFET. For VD  VDsat, the drain current remains constant.
For a given VG : ID increases linearly with VD then saturated
The dashed line : locus of the drain voltage VDsat (ID approach a max value)

19. Consider linear and saturation regions (for small VD)
Threshold voltage VT :
Channel conductance gD :
Transconductance gm :

20. TYPES OF MOSFET
Cross section, output, and transfer characteristics of four types of MOSFETs.