Presentation is loading. Please wait.

Presentation is loading. Please wait.

G.-F. Dalla Betta1, G. Batignani2, L. Bosisio3,

Published byMelvin Leonard Modified over 6 years ago

Similar presentations

Presentation on theme: "G.-F. Dalla Betta1, G. Batignani2, L. Bosisio3,"— Presentation transcript:

1 Monolithic Integration of Detectors and Transistors on High-Resistivity Silicon
G.-F. Dalla Betta1, G. Batignani2, L. Bosisio3, M. Boscardin4, P. Gregori4, C. Piemonte4, L. Ratti5, G. Verzellesi6, N. Zorzi4 1 INFN Trento and University of Trento,Italy 2 INFN Pisa and University of Pisa, Italy 3 INFN Trieste and University of Trieste, Italy 4 ITC-irst,Trento, Italy 5 INFN Pavia and University of Pavia, Italy 6 INFN Trento and University of Modena/Reggio Emilia, Italy

2 Process development at ITC-irst
Outline Introduction Process development at ITC-irst Transistor description: Experimental results Conclusions n-JFET (tetrode, triode) n-MOSFET npn BJT

3 Introduction Front-end electronics embedded on the detector substrate
can provide better noise performance and easier assembly, at the expense of process complexity and cost Normally worth for low capacitance detectors only Pioneering work in this field dates back to late 80’s: MPI Munich & BNL (for drift detectors), LBNL (detector compatible CMOS process for pixels) Most successful developments: fully depleted CCDs and DEPFET talk by J.Velthius

4 Process development at ITC-irst
It all started as a major technological challenge: first step toward becoming a primary technological partner for INFN The process development went on in the framework of few national projects (INFN and MIUR), mainly device oriented When device performance improved, we could start to identify suitable applications Current activity is oriented to: g-ray scintimammography (PIN diode + tetrode JFET) X-ray imaging (JFET-MOSFET active pixels) Radon monitoring (BJT)

5 Fabrication technology overview
Starting material: HR Si, 4”, <111>, n-type P-doped poly-Si gettering (back-side) Deep implantations (p-well, n-channel) Active area & poly-Si (low- and high-doping) Shallow implantations Interconnections (metal 1, metal 2) Standard steps Dedicated steps

6 2 options (different doping profiles)
n-channel p-well p-well n- Si substrate b) BJT (by product) a) JFET p+ n-ch. p-well n- sub. n+/n-ch. p-well n- sub. Base Collector Top-gate Bottom-gate Emitter

7 Additional steps do not degrade the process quality
Process parameters Data from last batch (JSD6, 2006) Parameter Typical Range Subst. doping concentration 2 – 5 × 1011 cm-3 Full depletion voltage 15 – 30 V Leakage current density 0.15 – 0.75 nA/cm2 Generation lifetime 50 – 250 ms Surface generation velocity 5 – 15 cm/s Field oxide charge density 3.5 – 4.0 × 1011 cm-2 Diode leakage current (thickness=300mm) Additional steps do not degrade the process quality

8 Transistors: tetrode n-JFETs (Lmin=6mm): it needs contact on top-gate
Enclosed layout drain source Bottom-gate 100/6 Top-gate (Lmin=6mm): it needs contact on top-gate

9 Tetrode JFET (W/L=100mm/6mm) Bottom-gate modulation
Allows for independent top-gate and bottom-gate control Transfer characteristics in saturation region (Vds=3V) Top-gate modulation Bottom-gate modulation

10 Tetrode JFET (W/L=100mm/6mm)
Output characteristics (Vbg=0) Input capacitance (Vbg=0) Low capacitance can match small area detectors

11 Detector head for scintimammography
Modular design Back side: CsI(Tl) scintillator + ARC 99mTc g-rays (140keV) CsI(Tl) scintillator 550nm photons PIN detector ~2000 electrons tile Front side: 8x8 PIN+JFET array (pitch 2mm) Tetrode JFET as CSA input transistor 1.6 cm 8x8 PIN+JFET matrix 1.6 cm Bump bonding to ASICs via LTCC interconnection

12 Transistors: triode n-JFETs
1000/4 Stripe interdigitated layout (Lmin=4mm) gate Top-gate & Bottom-gate shorted at the implant level drain source

13 Triode JFET (W/L=1000mm/4mm) Transfer characteristics (Vds=3V)
Input capacitance Due to bottom gate contribution, larger transconductance, but also larger capacitance (and gate current)

14 Triode JFET (W/L=1000mm/4mm) Noise spectrum (Vds=3V)
White noise (Vds=3V) White noise close to theoretical value (normal RGG’), Very good low-frequency noise behavior

15 Benchmark: JFET-based CSA
Monolithic part Equivalent Noise Charge (with 8th order semigaussian unipolar shaper) + external passive components Good ENC, in spite of large Cstray from the test board

16 Transistors: n-MOSFETs
Enclosed layout (Lmin=4mm) S&D self-aligned to poly-Si gate. 125/5 gate well source drain

17 Transfer characteristics Output characteristics
NMOS (W/L=125mm/5mm) Transfer characteristics (Vds=0.1V) Output characteristics Static characteristics are good enough to implement basic circuit functions

18 Example: current mirror
GND D1 D2 Max. Error 7% Max. error 4% Vd2=3V

19 Fully integrated CSA 650 mm Bias/Feedback 900 mm JFETs

20 Active pixel arrays (1) On pixel (3T-like APS)
P-well/substrate detector Punch-through Reset Address: M1 Source follower: J1 Column pull-down: J2 Readout: DDS stage

21 Only one collecting electrode
Active pixel arrays (2) 235 mm 4 mm Pixel J2 235 mm Pixel matrix 6 mm DDS J1 M1 RES Only one collecting electrode

22 Two emitter profiles and different layouts possible
Transistors: npn BJTs Two emitter profiles and different layouts possible Emitter area 0.01mm2 base emitter

23 Deep emitter npn BJT (AE=0.01mm2)
Current gain (b) Very high gain (~600) allows for radiation detection with a simple setup (load resistor only) … Transient response … but it needs bias to obtain a time constant of ~ 10s of ms. Without bias

24 a particle counter particles from 239Pu source (with 150 kW Rload)
scope R L Vbias particles from 239Pu source (with 150 kW Rload) Rpoly~100MW (must be >>rbe) Interesting for Radon monitoring with an extremely simple setup

25 Conclusions We have reported on recent results from the development of detector-compatible transistors at ITC-irst Devices feature good characteristics that are promising in view of full detector system implementations With last batch, we have started to focus on some applications The prototype functional tests are under way The technology is available to interested application-oriented partners

26 Additional slides

27 Radiation damage effects
Single JFETs (1000/4) irradiated with neutrons Gate current (Vgs=0, Vds=3V) Noise spectrum (Id=250mA, Vds=3V) Increase of gate current (proportional to fluence) Lorentzian noise contributions appear

28 Irradiated CSA: ENC prediction
Based on input JFET characteristics (1000/4) Minor effect of Lorentzian noise Large effect of gate current increase and related need of lower RF value Should be better with tetrode JFET (lower current from top-gate alone)

29 Allows for multi-element
BJT biasing: pnp BJT Epnp Cnpn Enpn Bpnp vcontr Allows for multi-element current biasing (current mirror) x IR laser pulses @ different Vcontr (with 20kW Rload) bias region x

Download ppt "G.-F. Dalla Betta1, G. Batignani2, L. Bosisio3,"

Similar presentations

Lecture Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (FET) MOSFET Introduction 1.

Lecture Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (FET) MOSFET Introduction 1.
MICROWAVE FET Microwave FET : operates in the microwave frequencies

MICROWAVE FET Microwave FET : operates in the microwave frequencies
of Single-Type-Column 3D silicon detectors

of Single-Type-Column 3D silicon detectors
Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course Field effect transistors.

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course Field effect transistors.
Metal Semiconductor Field Effect Transistors

Metal Semiconductor Field Effect Transistors
The metal-oxide field-effect transistor (MOSFET)

The metal-oxide field-effect transistor (MOSFET)
Week 8b OUTLINE Using pn-diodes to isolate transistors in an IC

Week 8b OUTLINE Using pn-diodes to isolate transistors in an IC
Chapter 28 Basic Transistor Theory. 2 Transistor Construction Bipolar Junction Transistor (BJT) –3 layers of doped semiconductor –2 p-n junctions –Layers.

Chapter 28 Basic Transistor Theory. 2 Transistor Construction Bipolar Junction Transistor (BJT) –3 layers of doped semiconductor –2 p-n junctions –Layers.
Semiconductor Devices III Physics 355. Transistors in CPUs Moore’s Law (1965): the number of components in an integrated circuit will double every year;

Semiconductor Devices III Physics 355. Transistors in CPUs Moore’s Law (1965): the number of components in an integrated circuit will double every year;
ENE 311 Lecture 10.

ENE 311 Lecture 10.
KIT – Universität des Landes Baden-Württemberg und nationales Forschungszentrum in der Helmholtz-Gemeinschaft KIT, Institut für Prozessdatenverarbeitung.

KIT – Universität des Landes Baden-Württemberg und nationales Forschungszentrum in der Helmholtz-Gemeinschaft KIT, Institut für Prozessdatenverarbeitung.
© 2013 The McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill 5-1 Electronics Principles & Applications Eighth Edition Chapter 5 Transistors.

© 2013 The McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill 5-1 Electronics Principles & Applications Eighth Edition Chapter 5 Transistors.
Fully depleted MAPS: Pegasus and MIMOSA 33 Maciej Kachel, Wojciech Duliński PICSEL group, IPHC Strasbourg 1 For low energy X-ray applications.

Fully depleted MAPS: Pegasus and MIMOSA 33 Maciej Kachel, Wojciech Duliński PICSEL group, IPHC Strasbourg 1 For low energy X-ray applications.
Field Effect Transistors

Field Effect Transistors
CERN, 14-16 November 2005 Claudio Piemonte RD50 workshop Claudio Piemonte a, Maurizio Boscardin a, Alberto Pozza a, Sabina Ronchin a, Nicola Zorzi a, Gian-Franco.

CERN, November 2005 Claudio Piemonte RD50 workshop Claudio Piemonte a, Maurizio Boscardin a, Alberto Pozza a, Sabina Ronchin a, Nicola Zorzi a, Gian-Franco.
Introduction to semiconductor technology. Outline –7 Field effect transistors MOS transistor ”current equation MOS transistor channel mobility Substrate.

Introduction to semiconductor technology. Outline –7 Field effect transistors MOS transistor ”current equation" MOS transistor channel mobility Substrate.
Technology Overview or Challenges of Future High Energy Particle Detection Tomasz Hemperek 2014 - 15.09.2014.

Technology Overview or Challenges of Future High Energy Particle Detection Tomasz Hemperek
Fig. 1: Cross section of a circular DEPMOS- FET pixel cell. Charges collected in the “in- ternal gate’ modulate the transistor current. DEPMOSFET team,

Fig. 1: Cross section of a circular DEPMOS- FET pixel cell. Charges collected in the “in- ternal gate’ modulate the transistor current. DEPMOSFET team,
The development of the readout ASIC for the pair-monitor with SOI technology ~irradiation test~ Yutaro Sato Tohoku Univ. 29 th Mar. 2010  Introduction.

The development of the readout ASIC for the pair-monitor with SOI technology ~irradiation test~ Yutaro Sato Tohoku Univ. 29 th Mar  Introduction.
Ljubljiana, 29/02/2012 G.-F. Dalla Betta Surface effects in double-sided silicon 3D sensors fabricated at FBK at FBK Gian-Franco Dalla Betta a, M. Povoli.

Ljubljiana, 29/02/2012 G.-F. Dalla Betta Surface effects in double-sided silicon 3D sensors fabricated at FBK at FBK Gian-Franco Dalla Betta a, M. Povoli.

Similar presentations

Ads by Google