1. FIRST REVIEW

2. Design and Implementation of High Speed VLSI Architecture for General
Linear Feedback Shift Register (LFSR)
Structures

3. INTRODUCTION
Linear Feedback Shift Register (LFSR) structures are widely used in digital signal processing and communication systems, such as BCH, CRC.
A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state.
One of the two main parts of an LFSR is the shift register (the other being the feedback function). A shift register is a device whose identifying function is to shift its contents into adjacent positions within the register or, in the case of the position on the end, out of the register. The position on the other end is left empty unless some new content is shifted into the register.

4. Basic LFSR architecture
FCS
………... x0 x1
Xn-1
x00
Xnn-1
x11 d
D Q CK
CLR
D Q CK
CLR
D Q CK
CLR
clock
clear
Divisor p0 … p1
Pm-1

5. Architectures for polynomial G (y)=1+y+y3+y5.
Data Y0 + Y1 Y2 + Y3 Y4 +

6. Linear Feedback Shift Registers (LFSRs)
These are n-bit counters exhibiting pseudo-random behavior.
Built from simple shift-registers with a small number of xor gates.
Used for:
random number generation
counters
error checking and correction
Advantages:
very little hardware
high speed operation
Example 4-bit LFSR:

7. Project Overview Identify the Architecture From the literature survey
Model the Architecture into RTL [register transfer level]modeling
Verify the functionality of Modeled architecture in MODELSIM®
Synthesis the verified design in Xilinx ISE®
Generation of Bit map file for Dump into Spartan 3E FPGA
Program the Bit map file into FPGA.

8. Advantages: LFSR takes less area than any other common counter.
High speed of operation than any other common counter

9. LFSR Applications Pattern Generators Counters
Built-in Self-Test (BIST)
Encryption
Compression
Checksums
Pseudo-Random Bit Sequences (PRBS)

10. LANGUAGES USED AND TOOLS
Verilog HDL
TOOLS REQUIRED:
Xilinx - Synthesis
MODELSIM – Simulation,

11. CRC concept I have a msg polynomial M(x) of degree m
We both have a generator poly G(x) of degree m
Let r(x) = remainder of M(x) xn / G(x)
M(x) xn = G(x)p(x) + r(x)
r(x) is of degree n
What is (M(x) xn – r(x)) / G(x) ?
So I send you M(x) xn – r(x)
m+n degree polynomial
You divide by G(x) to check
M(x) is just the m most signficant coefficients, r(x) the lower m
n-bit Message is viewed as coefficients of n-degree polynomial over binary numbers
n bits of zero at the end
tack on n bits of remainder
Instead of the zeros

12. Galois Fields - the theory behind LFSRs
LFSR circuits performs multiplication on a field.
A field is defined as a set with the following:
two operations defined on it:
“addition” and “multiplication”
closed under these operations
associative and distributive laws hold
additive and multiplicative identity elements
additive inverse for every element
multiplicative inverse for every non-zero element
Example fields:
set of rational numbers
set of real numbers
set of integers is not a field (why?)
Finite fields are called Galois fields.
Example:
Binary numbers 0,1 with XOR as “addition” and AND as “multiplication”.
Called GF(2).
0+1 = 1
1+1 = 0
0-1 = ?
1-1 = ?

13. Galois Fields - The theory behind LFSRs
Consider polynomials whose coefficients come from GF(2).
Each term of the form xn is either present or absent.
Examples: 0, 1, x, x2, and x7 + x6 + 1
= 1·x7 + 1· x6 + 0 · x5 + 0 · x4 + 0 · x3 + 0 · x2 + 0 · x1 + 1· x0
With addition and multiplication these form a field:
“Add”: XOR each element individually with no carry:
x4 + x x + 1
+ x x2 + x
x3 + x
“Multiply”: multiplying by xn is like shifting to the left.
x2 + x + 1
 x + 1
x3 + x2 + x x

14. Galois Fields - The theory behind LFSRs
These polynomials form a Galois (finite) field if we take the results of this multiplication modulo a prime polynomial p(x).
A prime polynomial is one that cannot be written as the product of two non-trivial polynomials q(x)r(x)
Perform modulo operation by subtracting a (polynomial) multiple of p(x) from the result. If the multiple is 1, this corresponds to XOR-ing the result with p(x).
For any degree, there exists at least one prime polynomial.
With it we can form GF(2n)
Additionally, …
Every Galois field has a primitive element, , such that all non-zero elements of the field can be expressed as a power of . By raising  to powers (modulo p(x)), all non-zero field elements can be formed.
Certain choices of p(x) make the simple polynomial x the primitive element. These polynomials are called primitive, and one exists for every degree.
For example, x4 + x + 1 is primitive. So  = x is a primitive element and successive powers of  will generate all non-zero elements of GF(16). Example on next slide.

15. BCH CODES
BCH codes are among the most widely used error-correcting codes
The encoders of BCH codes are conventionally implemented by a linear feedback shift register (LFSR) architecture.
BCH code with the following parameters:
n = 2m − 1
n − k ≤ mt
d min ≥ 2t + 1

16. Block Diagram for Modified BCH Encoding

17. Encoding circuit for a (n, k) BCH code

18. Three step implementation of BCH(255,233) Encoding

19. Improved Three Step Implementation of Bch(255,233)Encoding

20. Improved Three Step Implementation of Bch(255,233)Encoding

21. Step1 of a modified BCH encoding

22. Step-2 Of a Modified BCH Encoding

23. Step-3 of a modified BCH Encoding

24. An LFSR example, (b) 3-unfolded version of LFSR

25. Basic steps for simulating a design in ModelSim
Create a working Library
Compile Design files
Load and Run simulation
Debug Results

26. XILINX Implementation Design Flow Chart
System Specifications
Initial Concept
Block Diagram
Architecture
Coding
VHDL/Verilog Modeling
Functional verification
Simulation
Generating net list
Synthesis

27. Serial Implementation 1+y+y3+y5

28. Parellel Implementation 1+y+y3+y5

29. Thank you