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Radiation Tolerant DC to DC Converters
ATLAS Upgrade Week CERN 10/11/2010 B.Allongue, G.Blanchot, F.Faccio, C.Fuentes, S.Michelis, S.Orlandi CERN – PH-ESE
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Outline DCDC converters for sLHC.
Radiation tolerant ASICs development status. Development of DCDC Plug-in-Boards. EMC properties. Conclusions. AUW Nov. 2010 G. Blanchot, PH/ESE
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Outline DCDC converters for sLHC.
Radiation tolerant ASICs development status. Development of DCDC Plug-in-Boards. EMC properties. Conclusions. AUW Nov. 2010 G. Blanchot, PH/ESE
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DC/DC converters for sLHC
Increased need for power at sLHC Increased number of channels = more power needed. Cabling density cannot be increased further on. Power losses cannot be increased further on. New powering schemes DC/DC converters offer a conventional solution to increase the delivery of power to the front-end. Radiation, magnetic field, material budget are specific constrains to impose custom designs. Front-end systems are sensitive to couplings: need to pay particular attention to EMI issues. AUW Nov. 2010 G. Blanchot, PH/ESE
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Case Study: Short Strip Tracker
SC and optoelectronics 10-12V Rod/stave Module 2 Converter stage2 on-chip Scheme based on 2 conversion stages: Stage 1: On Module Buck DC/DC converter Stage 2: On Chip Switched Capacitor Development of buck converter prototypes at CERN Radiation tolerant DC/DC ASICs. EMC and board optimization. Production of sample converters for systems. Detector Let’s se an implementation example, Hybrid controller Intermediate voltage bus(ses) 10-12V Converter stage 1 block AUW Nov. 2010 G. Blanchot, PH/ESE
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Outline DCDC converters for sLHC.
Radiation tolerant ASICs development status. Development of DCDC Plug-in-Boards. EMC properties. Conclusions. F. Faccio AUW Nov. 2010 G. Blanchot, PH/ESE
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Embedded functionalities of different prototypes
AMIS2 IHP1 IHP2 Next✱ Full control loop ✓ Dead times’ handling Fixed Adaptive (QSW) (QSW and CCM, sharp transition) (QSW and CCM, smooth transition) On-chip regulator(s) No Soft Start Simple RC Simple RC with comparators Full sequence with comparators State machine Over-I protection Over-T protection Under-V disable ✱Full design complete at schematic level (including start-up and protection features simulated with a behavioral model for the converter) AUW Nov. 2010 G. Blanchot, PH/ESE
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IHP1 and IHP2 IHP1 First prototype in the IHP 0.25μm technology - no on-chip regulators and bandgap voltage (Vbg) generator Excellent performance IHP2 Includes all on-chip regulators and Vbg generator, plus over-current protection It uses ‘new’ LDMOS transistors (different than IHP1) - change forced by transition from generation 2 to 3 at IHP High efficiency, but 2 relevant problems observed Additionally, ‘new’ LDMOS have radiation tolerance issues IHP1 IHP2 AUW Nov. 2010 G. Blanchot, PH/ESE
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Problems observed on IHP2
Although working well at first, DCDC samples destructively failed with no warning when switching conditions were modified (Iload, Vin) or randomly during measurements This has been eventually traced to the onset of latch-up triggered by the cyclic forward- biasing of the drain-bulk diode of the NMOS power transistor (normal behavior in a synchronous DCDC) The problem was not observed in IHP1, indicating that the ‘new’ LDMOS inject significantly more current in the substrate Corrective actions are possible at the layout level, but need to be verified Samples irradiated with protons are not functional already after an integrated fluence of 1E15 p/cm2 Measurement of individual transistors showed that the ‘new’ LDMOS are much more damaged by protons than the generation 2 devices tested in (in particular the PMOS and the Isolated NMOS) AUW Nov. 2010 G. Blanchot, PH/ESE
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SEB and SEGR test results (IHP Generation 3)
Single Event Burnout (SEB) and Single Event Gate Rupture (SEGR) are potentially destructive events threatening high-voltage transistors in a radiation environment Dedicated study done on ‘new’ IHP LDMOS using a heavy ion beam A large number of SEB events has been observed for N LDMOS Sensitivity observed for Vds as low as 8V and for Heavy Ion LET as low as 10 MeVcm2mg-1 No event observed for PMOS during the full test (up to 13V) SEGR No sensitivity measured on N and PMOS Limit cross-section, no SEB observed Cross-section (cm2) LET (MeVcm2mg-1) AUW Nov. 2010 G. Blanchot, PH/ESE
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Conclusion on IHP2 With respect to the former prototype IHP1, the differences that led to relevant consequences were: The change of N and P LDMOS to the ‘new’ Generation3 transistors The use of Isolated NLDMOS transistors The integration of the on-chip regulators and duplication of the buffers driving the switches (all other layouts that might contribute to the observed problems remained unchanged) As a result, the converter suffers destructive failures due to latchup and is not tolerant to the required level of displacement damage Moreover, NLDMOS transistors suffer SEB potentially leading to catastrophic failure in the DCDC (we ignore whether this would be an issue for Generation 2 transistors) Further design of a full DCDC converter in the 0.25μm technology has to wait until an appropriate set of LDMOS transistors has been qualified and brought to a sufficient level of maturity. AUW Nov. 2010 G. Blanchot, PH/ESE
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AMIS2 Former prototype in the ‘backup’ 0.35um technology (design done in 2008) Simple design without on-chip regulator, but proved to be working well and reliably (extensively used in system tests) Lower efficiency than IHP1 and IHP2 Radiation tolerance to both TID and displacement damage verified to high levels - but no data was available for SEB-SEGR AUW Nov. 2010 G. Blanchot, PH/ESE
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SEB test of AMIS2 Heavy Ions beam irradiation test performed
Measurements done on both: Individual NLDMOS transistor with protection resistor in series (and external comparator) Full switching AMIS2 converter (increasing Vin from 6 to 12V, Vout=2.5V, f=1MHz, L=500nH, without load or with 0.5A load in some conditions). 2 samples exposed. No SEB observed in any of the tests with LET of 21 or 31 MeVcm2mg-1, up to a maximum Vds of 12V The 0.35μm technology is fully radiation qualified and adequate for the integration of a DCDC converter AUW Nov. 2010 G. Blanchot, PH/ESE
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ASICs Status Summary Three prototype DCDC converter ASICs, with increasing complexity, have been produced and tested The chosen circuit solutions have been verified and improved leading to higher efficiencies and getting closer to a final complete design (with all protection features) The design methodology has been improved with the addition of a behavioral simulation approach considerably shortening simulation time (and allowing study of system stability) With the introduction of ‘new’ LDMOS transistors, and of increased on-chip functionality (regulators), the most recent prototype in the 0.25μm technology has problems incompatible with a final reliable and radiation-tolerant design Further developments in this technology have to wait the qualification and maturity of a set of LDMOS transistors Meanwhile, the successful full radiation qualification of the AMIS2 DCDC in the 0.35μm technology indicates a safe path for the rapid development of a radiation-tolerant converter. AMIS3 has been submitted (due 02/2011), AMIS4 is under development. AUW Nov. 2010 G. Blanchot, PH/ESE
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Outline DCDC converters for sLHC.
Radiation tolerant ASICs development status. Development of DCDC Plug-in-Boards. EMC properties. Conclusions. AUW Nov. 2010 G. Blanchot, PH/ESE
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Noise Optimized Plug-in-Boards
DCDC plug-in board to be used with systems, providing: A compatible form. Compact design. Power interface: connector or bonds. In some cases: control logic (ON/OFF + PowerGood). Control of the noise sources for lower conducted and radiated couplings: Understanding of how electromagnetic fields are emitted from power loops and switching nodes. Layout that minimizes the conducted and radiated noise. Shielding: to cancel E field couplings with front-end systems. to mitigate the radiated B field down to compatible levels . Cooling: A thermal interface must be provided for cooling. Several DCDC-PIB have been designed and produced (or in production now): AMIS2_DCDC: 2 versions with AMIS2 radiation tolerant ASIC, implementing noise cancellation techniques. 10V down to 2.5V rated 2A for the 0.13um ABCN or any other low power module. SM01C: using a commercial LT3605 chip similar to AMIS2, 60 boards available by end 2010. 10V down to 2.5V rated 5A for the 0.25um ABCN modules in use today, with connector. STV10: same design as SM01C, for bonded connections on the ATLAS stavelet, ready for prod. AUW Nov. 2010 G. Blanchot, PH/ESE
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Noise Optimized Plug-in-Boards
PROTO5 AMIS2 SM01B Enable Pgood Vin GND Vout Board size reduction down to 26mmx13.5mmx9mm. SM01C is 28.4x13.5x9mm for ATLAS supermodule. Increased switching frequency: 2 MHz on AMIS2, 3 MHz on SM01B. Custom coil (industrially made): 250nH that will stand straight onto the AMIS2 ASIC. Custom shields: PE boxes painted with Cu loaded varnish; plastic boxes with Cu coating under study. Efficiencies above 80% achieved. SM01B reaches 87% at 2A, and is still at 80% for 4A load current at nominal input voltage. SM01B AUW Nov. 2010 G. Blanchot, PH/ESE
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Outline DCDC converters for sLHC.
Radiation tolerant ASICs development status. Development of DCDC Plug-in-Boards. EMC properties. Conclusions. AUW Nov. 2010 G. Blanchot, PH/ESE
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Radiated Magnetic Field
Switching freq. = 1 MHz L = 350 nH Load = 1A. PROTO5 1 3 5 AMIS2 SM01B The radiated magnetic field is measured along X, Y and Z axes with a 1cm loop probe over a grid. The vector magnitude is computed. [dBµA/m] Unshielded Shielded Comment PROTO5 115 Shielded coil only SM01B >120 <100 Non EMC optimized layout AMIS2 110 EMC optimized layout AUW Nov. 2010 G. Blanchot, PH/ESE
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AMIS2DCDC Conducted Noise
ATLAS Limit ATLAS Limit Class A Limit Class A Limit Class B Limit Class B Limit To further mitigate the radiated fields, electric and magnetic near field couplings that take please within the DCDC board and its components were modeled. Based on this, noise cancelling routing and placement topologies were implemented onto a new generation of converters using the AMIS2 ASIC. On this, a shield is added. Compared to Proto5: AMIS2_DCDC has more than 20dB less CM noise, of about 300 nA at 3 MHz. Switch Frequency is now 3 MHz: there are less harmonic peaks in the sensitive band. Now complies with Class B with more than 20dB of margin. The DM noise has also been reduced. Barely visible. Two peaks at 3MHz and 6 MHz only, with less than 300 nA amplitude. Now complies with Class B with more than 25dB of margin. AUW Nov. 2010 G. Blanchot, PH/ESE
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Optimized AMIS2 DCDC on UniGe Module
AMIS2_DCDC, shield: ENC Sigma Reference: Conducted: Radiated Corner: Radiated Top: Conducted noise test VCC and VDD are each powered from two different DCDC converter, without regulator on VCC. The AMIS2-PIB, induces 10% more noise with respect to the reference configuration, when two converters are place straight on top of the hybrids. The improvement is very significant, and is in line with the noise reduction observed on the reference test stand (CM and DM noise). Radiated noise at corner Radiated noise on top of hybrid AUW Nov. 2010 G. Blanchot, PH/ESE
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SM01B DCDC on UniGe Module
SM01B shielded: ENC Sigma Reference: 3cm on bonds: Radiated Top: Reference noise 3cm from bonds Radiated noise on top of hybrid VCC and VDD are each powered from the same DCDC converter, with regulator on VCC for the analog power of the ABCN chips. The SM01B, induces less than 2% more noise with respect to the reference configuration, when the converter is placed straight on top of the hybrids. SM01B radiates more than AMIS2DCDC but less noise is observed: 2 AMISDCDC vs 1 SM01B. Setups are slightly different: distance from DCDC to hybrid probably larger for SM01B. No analog regulator for the AMIS2DCDC test. It is in both cases an excellent performance for an extreme placement of converters. AUW Nov. 2010 G. Blanchot, PH/ESE
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Conclusions A radiation tolerant technology is now qualified, resulting in AMIS2 ASICs available for applications that require less than 2.5V. Further developments going on with IHP for secodn source technology. AMIS2 was succesfully integrated in a low noise plug-in module compatible with a tracker front-end prototype. Alternatively, plug in converters based on the commercial LT3605 chip have been designed for application that require today 5A 2.5V, with perfromances very close to AMIS2 but not radiation tolerant. 60 boards SM01C in production now, 20 due mid november, 40 due mid december. Suitable for Supermodule tests. A design to be bonded onto stavelets is now ready for production. More information in the Staves session. AUW Nov. 2010 G. Blanchot, PH/ESE
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