1. Sector logic firmware and G-link Merger board designs
H.Kurashige Kobe Univ.
2013/9/4

2. Endcap Sector Logic : current
Each board covers two Endcap sectors
 covers 1/24 = 2 x 1/48 of each side
12 G-Link Inputs from BW
2 from Hpt Wire per sector
1 from Hpt Strip per sector
4 G-Link Inputs
from Inner Station
 covers 1/6 = 4 x 1/24
Each G-link from one EI/FI SLB contains 15 bits hit info. per link
8 bits for FI
7 bits for EI
2013/9/4

3. Endcap Sector Logic : block diagram (current)
TGC Big-Wheel
TGC Inner-station
2013/9/4

4. Endcap Sector Logic : block diagram for Tile-m
TGC Big-Wheel
coin. [ TGC_EI/FI + TILE ]
TGC
Inner
From Merger
No additional Latency is expected with Tile-m
TILE-μ
Delay
2013/9/4

5. Endcap Sector Logic : Tile-m
Each board covers two Endcap sectors : 1/24
12 G-Link Inputs from BW
3 G-Link for Inner Station from merger board
51 bits
= 3 FIs + 4 EIs (partially)
1 G-Link from Tile-m
16bits
= 4-modules
x 2-threshold
　 x 2-types of sum
Delay for timing adjustment
between BW, Inner station and
Tile-m is implemented
at the first stage.
4 x Inner Sectors
4 x Tile Modules
2 x Endcap
Sectors
2013/9/4

6. Tile-m coincidence
4 Tile-m Modules are used for each Sector Logic board
3 Tile-m modules for each trigger sector
Trigger condition for Tile-m are set by using LUT in FPGA
No additional latency is expected
as far as Tile-m signal comes by 41 ticks
Fiber bundles can be used between Tile-m Module and SL
12 fibers per SL crate
2013/9/4

7. G-Link Merger Board Each Board (VME 6U) covers Octant
Fiber IN : 5
Fiber Out: 9 (3fibers x 3 SL boards)
Latency is not changed because Inner Station signals arrive ahead of BW signals
20 boards (8[A]+8[C]+spare)
will be manufactured
125 k CHF in total
Production: 100k CHF
Design 15k CHF
VME 6U crate : 5k CHF
SBC : 5k CHF
2013/9/4

8. Plan for developments: SL
Firmware for SL
We will start it soon (within 1 month)
after we have finished tests of new firmware
for Inner Station
DAQ software need to be modified slightly
Several control registers will be added
No specific difficulties are foreseen
First version will be obtained and be tested
by the end of this year
Manpower
Hisaya (Kobe) + 1 student
2013/9/4

9. Plan for developments: SL
Test setup for SL in Bat. 188
Pulse Pattern Generator emulates signals from BW (Hpt) and Inner Station
Check trigger and readout data
2013/9/4

10. Plan for developments: Merger board
G-link Merger board
We have started board design
Developments of firmware for on-board FPGA will start soon
The patterns of merging signals together with G- link controller are implemented in the firmware.
VME protocol is used only for downloading FPGA firmware. No DAQ software is necessary.
First prototype will appear by the end of this year
Manpower
Toshi/Masaya (Kyoto) + 1 student
2013/9/4