1. EEE4084F Digital Systems Review of EEE4084F 2017 Lecturer:
Simon Winberg

2. Lecture Overview Lecture content covered Readings, seminars, chapters
EEE4084F

3. Digital Systems
Lecture Review
EEE4084F Digital Systems

4. Lecture 1
Nothing of Lecture 1 is examined

5. Lecture 2 Terms. Golden Measure, Validation and Verilfication
Temporal & spatial computing
Correlation
Simply benchmarking

6. Lecture 3 Review of quiz 0 (skip) UML blurb (can skip)
Parallel computing fundamentals
Amdahl’s Law
Base Core Equivalents (BCEs)
Calculating performance using BCEs

7. Lecture 4 Temporal and Spatial Computation
Parallel computing programming
Automatic parallelism
Performance benchmarking
Wall-clock time
Benchmarking : what to test
Metrics of performance analysis
Trends

8. Lecture 5 Performance benchmarking consideration Timing in C
C Example using precision timing
HDL example to contemplate
Parallel Programming Models
Parallel System Approaches
Data vs. Task Parallel
Types of Data Dependences
Using a mutex
Shared memory partitioning approaches

9. Lecture 6 Classic parallel programming techniques
Processor Architecture Types
Von Neumann
Class activity
Flynn’s Taxonomy
Memory access architectures
Case Studies of classic microprocessor/ microcontroller architectures
Additional readings

10. Lecture 7 Where work is done, division of labour HPEC management
HPEC development process
Setting system objectives
Costs & risks
Monitoring progress
Documentation
Effort, Productivity and Progress

11. Lecture 8
Brief overview of OpenCL
OpenCL won’t be in the exam

12. Lecture 9
Conceptual assignment
won’t be in the exam

13. Lecture 10
Seems to have been skipped

14. Lecture 11 Steps in designing parallel solutions:
Step 1: understanding the problem
Step 2: partitioning
Step 3: decomposition & granularity

15. Lecture 12 Steps in designing parallel solutions Step 4: communication
Factors related to Communication
Cost of communications
Latency vs. Bandwidth
Baud rate vs. Bandwidth
Effective bandwidth
Visibility of Communications
Synchronous vs. asynchronous
Scope of communications
Collective communications
Efficiency of communications

16. Lecture 13 DeepQA – a HPEC case study
Designing parallel programs (cont.)
Steps 5-8 (see later slide showing steps)
Step 5: Identify data dependencies
Step 6: Synchronization
Step 7: Load balancing
Step 8: Performance analysis and tuning

17. Lecture 14
Cloud computing
Virtualization

18. Lecture 15 MPI vs. OpenMP Data parallel Message Passing (MP) model
Message passing implementations
Two ‘MP’ households
Intro to MPI & OpenMPI
Intro to OpenMP
MPICH

19. Lecture 16
YODA Project introduction
Not examined

20. Lecture 17 Programmable Logic Chips ASICs vs. Programmable Chips
FPGA families
(ignore project stuff)

21. Lecture 18
FPGA Interns
FPGA vs CPU performance

22. Lecture 19 Why Verilog? Basics of Verilog coding Exercise
Verilog simulators
Intro to Verilog in ISE/Vivado
Test bench
Generating Verilog from Schematic Editors
(If you aren’t so strong in Verilog it doesn’t matter too much as I usually give the option to give answers in VHDL if it is preferred)

23. Lecture 20 More Verilog Brief recap Busses and endianess
Functions in Verilog
Implementing state machines
Constraints
UCF Files
statemachine

24. Lecture 21 More Verilog When to use assign
Blocking & non-blocking simulation and potential pitfalls
The unconditional always
Configuration architectures
Digital signals, Interface basics, Using latches

25. Lecture 22 Interconnection on-chip bus topologies
Interfacing standards
A look at Wishbone and how it works
Standard memory interfaces
DMA transfers
Memory types

26. Lecture 23 Softcore processors Case studies: Xilinx Microblaze
You don’t really need to know know much specifics about soft core processors,
But you should know their names, important standards / bus standards and structures they support.
Softcore processors
Case studies:
Xilinx Microblaze
Xilinx Picoblaze
DUGONG : not examined
[Optional: Altera/Intel NIOS2] : not examined

27. Lecture 24
RC Platform Case Studies part 1 of 2: Tools and toolchain considerations
Detailed case study of RC / heterogeneous computer architecture
Purpose of this lecture
Cell Processor
Cell Processor Programming models
IBM Blade

28. Lecture 25
Not examined
RC Platform Case Studies part 2 of 2: RC FPGA-based case studies
Large-scale FPGA-based RC system examples
PAM, VCC, Splash
Small-scale FPGA-based RC system examples
PRISM
Algotronix CAL, XC620,
Cray Research XD1,
SRC
Silicon Graphics RASP

29. Lecture 26 MIPS and FLOPS are not enough… C  HDL automatic conversion
Overview of conversion process
Limitations
Scenario
Mapping C to HDL behavioural
Some tools

30. Exam safety nets
EEE4084F

31. Verilog Cheat Sheet

32. Formulas Cheat Sheet

33. Other cheat sheets If needed MPI cheat sheet OpenCL cheat sheet
HandleC cheat sheet

34. Chapters / Seminar Review
EEE4084F Digital Systems
Please see announcement concerning the chapters (copied on next slide)

35. EEE4084F Book Chapter Exam Syllabus 2017
Pages of text book examinable
S2 Ch1 3-11; 13 (but for this chapter you only really need to read over from pp 3 to half-way though pg 5).
S2 Ch ; 24 (but from sect 2.4 that starts on pg 23) - 27
S3 Ch
Ch sect (but 4.4 you can look over but no need for specifics)
S4 Ch ; 88-89;
S6 Ch7 ADC & DAC ; (don't need to worry about the trends discussed in but you need to know what ENOB etc is)
S7 Ch ; ; 207 (from sec 9.8) (inc )
S7 Ch
S9 Ch ; ; 274; (excluding and )
S8 Ch i.e. all relevant
S5 Ch15 Can skip 15.2 and 15.3 except Amdahl, can skip most of 15.4 and (seminar covers important aspects pretty well)
Ch (but you need not know the specifics, e.g. info about the various math libs discussed)  not examined
Ch (but you can skip the detailed case studies re radar and other specialized details -- the main aspects were anyway covered in the lectures)  have a brief look, covered already in lectures / pracs
S10 Ch Should know about the principles, won't be asked to remember in detail for instance how a turbo encoder works but the sort of question on this topic may involve a case study where you'd need to provide comms advice for instance.
S11 Ch ; 473;
S1 Berkeley paper (Seminar #1)
R01 Berkeley Landscale of Parallel Computing Research.pdf
Relevant pages: pp 1-2 ; pp 3-8 (don't need to know what each of the 7 dwarfs are); pp (composition of drawfs is relevant in terms of discussing dwarfs) excl. Sect 4.3; pp (ignore 4.1.2); pp Note that much of the content of this paper is covered in more detail in the textbook and lectures.

36. Exam Prep
Lectures,
Readings,
Seminars &
Chapters

37. End of EEE4084F Lectures! Enjoying the Vacation!!!
Good luck with the exams
And look forward to…
Enjoying the Vacation!!!