1. Introduction
Tsung-Yi Wu

2. IC
VLSI IC
very-large-scale integration IC

3. IC
PowerPC: 6.9 Million Transistors

4. IC IC Evolution SSI  MSI  LSI VLSI  ULSI?
Simple Chip  SOC (System On a Chip)

5. IC Process Technology 0.35 um0.25 um0.18 um0.13 um90 nm
Aluminum  Copper
Wafer Size
6 inches  8 inches  12 inches

6. IC Alpha 21264: 15 million Pentium Pro: 5.5 million Moore’s Law
PowerPC 620: 6.9 million
Alpha 21164: 9.3 million
Sparc Ultra: 5.2 million
Moore’s Law
IC improvements:
Die size: 10-20% per yr
Transistor density: 35% / yr
Moore’s Law: Number of transistors per chip increases 4x every 3 years.
Adapted from (Prof. Patterson’s CS252S98 viewgraph). Copyright 1998 UCB

7. IC
Intel Processors (Area)

8. IC
Intel Processors (Performance)

9. IC
IC Product Market Shares

10. IC
IC Product Market Shares

11. Design Flow
Flow
Idea
Design
Manufacture
Testing
Production

12. Design Flow Evolution on Design Techniques
Layout Design  Gate Design  RTL Design
RTL Design  Behavioral Design ? A
Out V DD
GND B
clk)
count = count + 1;

13. Design Flow
Design Techniques

14. Design Flow Design Tasks System Logic Physical Idea Design Manufacture
Testing
Production
System
Logic
Physical

15. Design Flow System Level Design High Level Design
Partitioning into hardware and software, co-design, co-simulation, etc.
Cost estimation, design-space exploration
High Level Design
More abstract than logic design (described by C, System C, etc.)

16. Design Flow Logic Design Schematic entry
Register-transfer level and logic synthesis
Gate-level simulation (functionality, power, etc)
Timing analysis
Formal verification

17. Design Flow Design Actions Synthesis Analysis Verification
increasing information about the design by providing more detail (e.g., logic synthesis, physical synthesis).
Analysis
collecting information on the quality of the design (e.g., timing analysis).
Verification
checking whether a synthesis step has left the specification intact (e.g., layout verification).

18. Design Flow Design Actions Optimization Design Management
increasing the quality of the design by rearrangements in a given description (e.g., logic optimizer, timing optimizer).
Design Management
storage of design data, cooperation between tools, design flow, etc. (e.g., database).

19. Logic Synthesizer translates RTL design to gate-level design.
Design Flow
Logic Synthesis
Logic Synthesizer translates RTL design to gate-level design.
RTL
clk)
count = count + 1; :
Logic Design
Gate-level Design

20. Design Flow Logic Synthesis
Logic synthesis programs transform Boolean expressions into logic gate networks in a particular library.
Optimization goals: minimize area, delay, power, etc
Technology-independent optimization: logic optimization
Optimizes Boolean expression equivalent.
Technology-dependent optimization: technology mapping/library binding
Maps Boolean expressions into a particular cell library.

21. Design Flow Logic Design Synthesizer
You set the goals (through constraints).
Large
Area
Small
Short
Delay
Long •

22. Design Flow Two-level: minimize the # of product terms
E.g. F = X & Y + X & Y’  F = X
Multi-level: minimize the #'s of literals, variables.

23. Design Flow Logic Synthesis F Decomposed / optimized network
Subject graph
Logic decomposition/optimization
NAND2/INV decomposition
Technology mapping

24. Design Flow
Physical Design
CMOS A
Out V DD
GND B
2-input NAND gate

25. Design Flow
Physical Design
Full Custom
Semi-Custom
Cell-Based (ASIC)

26. Design Flow Physical Design Full Custom
Using Full Custom Design we can get exactly what we want.
However:
1) Complex to design
2) Takes weeks to fabricate
3) No economies of scale
4) How do we automate
the mapping?

27. Design Flow
Physical Design
Cell-Based

28. Design Flow
Physical Design
Cell-Based FP
Place
Route

29. Design for Manufacturing
Design Flow
Astro Flow
Synthesis
Placement
CTS
Routing
Floorplanning
Design Setup
Timing Setup
Design for Manufacturing

30. Design Flow Floor-plan Design Hierarchy {L,M,N} {C} {O,P} {I,J,K}
{G,H}
{F}
{L,M,N}
{C} { O , P }
{I,J,K} G H
{F}

31. Design Flow
Floor-plan: Examples
Control
ALU
Cache FP
Reg
Mult

32. Design Flow Floor-plan: Examples Core placement areaIP
ROM
RAM
The location of the core, periphery areas and the P/G grid, define the Floorplan of the chip.
Rings
P/G Grid
Straps
Periphery area

33. Design Flow Placement and Routing Routing Placement {L,M,N} {C} {O,P}
{I,J,K}
{G,H}
{F}
Routing
Placement

34. Design Flow Placement Example Flipped Cells Abutted Rows
INV1
VSS
VDD
JKFF
DFFSR1
AOI221
AND2
BUF2B
NOR3
NA21
XOR2
MUX21
Abutted Rows
Flipped Cells
BUF2B
VDD
VSS
MUX21
INV1
NOR3
XOR2
NA21
AND2
DFFSR1
AOI221
JKFF
Non-abutted Rows

35. Timing-critical cells placed together
Design Flow
Timing-Driven Placement
Cells in a timing-critical path are placed close together to reduce routing-related delays
BUF2B
VDD
VSS
MUX21
INV1
NOR3
XOR2
NA21
AND2
DFFSR1
AOI221
JKFF
Placement Rows
Timing-critical cells placed together

36. Un-buffered clock tree
Design Flow
Clock Tree Synthesis
synthesize buffers and balanced clock tree network
route buffers and optimize the clock tree
Un-buffered clock tree
Buffered/balanced
clock tree

37. Design Flow
A Non-Zero-Skew Clock Tree
clock skew = 40 – 12 = 28 units

38. Design Flow
A Zero-Skew Clock Tree
clock skew = 0

39. Design Flow
H-Tree Construction
Tapping point
Clock source

40. Design Flow
MMM (Method of Means and Medians) Algorithm

41. Route wires between pins
Design Flow
Routing Example Z A1 A2
OR2A3 A
INVA4
Abstract A Z A1 A2
Place the cells
Route wires between pins
OR2A3
INVA4

42. Design Flow Channel-based Routing Cells are abutted in rows
BUF2B
VDD
VSS
MUX21
INV1
NOR3
XOR2
NA21
JKFF
DFFSR1
AOI221
AND2
Channel-based Routing
Cells are abutted in rows
Routing is in channel area only
Overall chip requires more area to allow for channels
Older P&R technology

43. Design Flow Area-based Routing Example Metal 1 is usually Horizontal
Metal 2 Vertical
Metal 3 Horizontal, etc
Metal 3
Stacked Vias
Metal 2
Oxide
Metal 1

44. Design Flow Timing-Driven Routing
Routing along timing-critical path is given priority:
Creates shorter, faster connections
Non-critical paths are routed around critical areas:
Reduces routability problems for critical paths
Does not impact timing of non-critical paths

45. Design Flow An Example Heap Verilog RTL Code always@(posedge clk)
begin
if (new_node_idx == 17) complete = 1;
else complete = 0;
end
reheapup ru1(new_node_idx,new_node_value,clk,go,done);
endmodule
module reheapup(new_node_idx,new_node_value,clk,go,done);
/* go 1->0->1 will trigger reheapup to work */
/* go must synchronize to clk */
/* If reheapup is done, the done signal will be set high */
input [7:0] new_node_value;
input [4:0] new_node_idx;
input clk,go;
output done;
reg [7:0] heap [15:1];
reg done;
reg [4:0] parent_idx, cur_node_idx;
reg [7:0] tmp;
if (! go)
done = 0;
cur_node_idx = new_node_idx;
if (new_node_idx < 16) heap[new_node_idx] = new_node_value;
else
if ((! done) && (cur_node_idx!=1))
parent_idx = {1'b0, cur_node_idx[3:1]}; /* divide 2 */
if (heap[cur_node_idx] > heap[parent_idx])
tmp = heap[parent_idx];
heap[parent_idx] = heap[cur_node_idx];
heap[cur_node_idx] = tmp;
cur_node_idx = parent_idx;
else done = 1'b1;
An Example
Heap
Verilog RTL Code

46. Design Flow Verilog RTL Code
module heap(node_value,clk,fill,complete);
input clk,fill;
input[7:0] node_value;
output complete;
reg complete;
wire [7:0] new_node_value;
reg [4:0] new_node_idx;
reg [7:0] data [15:1];
reg [4:0] cnt;
reg go;
wire done;
assign new_node_value = data [new_node_idx];
clk)
begin
if (!fill)
cnt = 0;
go = 0;
new_node_idx = 1;
end
else
if (cnt != 16) cnt = cnt + 1;
if (cnt < 16) data[cnt] = node_value;
if ((!go) && cnt == 16 && new_node_idx != 17) begin
go = 1;
new_node_idx = new_node_idx + 1;
else if (done==1) go = 0;
else if (new_node_idx == 17) go = 0;

47. Design Flow
Gate Level

48. Design Flow
Floor-Plan

49. Design Flow
Placement

50. Design Flow CTS Cell Insertion
< CLKINVX3 \ru1/U19 (.A(\ru1/n323 ), .Y(\ru1/n522 ));
< CLKINVX3 \ru1/U18 (.A(\ru1/n304 ), .Y(\ru1/n544 ));
< CLKINVX3 \ru1/U17 (.A(\ru1/n390 ), .Y(\ru1/n400 ));
< CLKINVX3 \ru1/U16 (.A(\ru1/n376 ), .Y(\ru1/n387 ));
< CLKINVX3 \ru1/U15 (.A(\ru1/n416 ), .Y(\ru1/n429 ));
< CLKINVX3 \ru1/U14 (.A(\ru1/n403 ), .Y(\ru1/n413 ));
< CLKINVX3 \ru1/U13 (.A(\ru1/n339 ), .Y(\ru1/n535 ));
< CLKINVX3 \ru1/U12 (.A(\ru1/n300 ), .Y(\ru1/n510 ));
< CLKINVX4 U12 (.A(n196), .Y(n197));
< CLKINVX4 \ru1/U4 (.A(\ru1/n507 ), .Y(\ru1/n208 ));
< CLKINVX8 U60 (.A(n202), .Y(n198));
---
> CLKINVX3 U12 (.A(n196), .Y(n197));
> CLKINVX3 U60 (.A(n202), .Y(n198));

51. Design Flow
CTS
Routing

52. Design Flow CTS Clock Skew Analysis
======== Detailed Clock Skew Report ============================
Clock: clk
Pin: clk
Net: clk
====================================================================
Pin Skew Phase Delay
clk
\cnt_reg[2]/CK
\cnt_reg[1]/CK
\cnt_reg[0]/CK
\new_node_idx_reg[3]/CK
\cnt_reg[3]/CK
\new_node_idx_reg[4]/CK
\new_node_idx_reg[2]/CK
\new_node_idx_reg[1]/CK
\cnt_reg[4]/CK

53. Design Flow
Routing

54. Design Flow
Routing

55. Design Flow
GDSII
Physical
design
Data
GDSII
Masks
Wafer

56. Mask layout flow

57. Design for Value Inject concept of function into mask flow
Selective OPC (Optical Proximity Correction)
Various levels of OPC depending on timing and yield criticality of features
Obtain desired level of parametric yield

58. No OPC Medium OPC Aggressive OPC
Design for Value
OPC
No OPC Medium OPC Aggressive OPC

59. Design Flow
Testing
Input
Output
0000
0001
0010 vs + =