1. EC Activities Status for LIU September 2017
Roger Barlow, Etienne Carlier, Gregor Gräwer, Christophe Lolliot, Steven Pavis, Marco Pimentel, Pieter Van Trappen
LIU and TE/ABT activities

2. PSB – BI.BSW All hardware @ CERN (including spare)
Christophe Lolliot
All CERN (including spare)
Ready for installation
Integration with WIC defined
DIC issued
DEC for BI.SMH to be generated

3. PSB – BI.DIS All hardware @ CERN (including spare)
Roger Barlow
All CERN (including spare)
Ready for installation
Test of individual electronics & controls sub-systems completed
Migration from FID to FIDS ongoing (Q4-2017)
867 test bench “carbon copy” of operational installation
Integration in control infrastructure ongoing (FESA)
Coordination of installation activities in BCER to further progress (internal and external)

4. PSB – BI.KSW All hardware @ CERN (Including spare)
Gregor Grawer
All CERN (Including spare)
Installation of full system (electronics & controls, pulse generators & magnets) in 865 for validation of one complete system
Required performance reached (400A +15% for high current & 40A +15% for low current)
Reliability test ongoing
Definition of API for integration in control infrastructure ongoing
Dynamic waveform control under implementation
Migration of low-level control from LabVIEW to Linux/FESA under study

5. PSB – BI.TKSTR All hardware @ CERN Ready for installation
Pieter Van Trappen
All CERN
Ready for installation

6. PS – PI.KFA45 Re-engineering completed
Steven Pavis
Re-engineering completed
Electronics and Controls architecture defined (including 5th generator system in 867)
Work on functional specification ongoing
Operational requirements under study
Specification infrastructure started
preDIC issued
DIC/DEC in preparation
CONS of key sub-components ongoing
Power supplies, capacitor bank, fast interlocking…
WU updated (to be uploaded)

7. PS – PI.SMH42 & PI.BSW42 Strategy defined
Marco Pimentel
Strategy defined
Added to ongoing PS-Complex Septa Electronics and Controls consolidation
Functional specification available
Production in progress
WU updated (to be uploaded)
DIC in preparation

8. SPS - SBDS Electronics & controls architecture defined
Pieter Van Trappen
Electronics & controls architecture defined
75% of hardware reused from existing system
Prototype of new hardware under test in 865 & 867
Power Trigger Module
TSU with locking on SPS Frev (will be tested on SBDS1 during run)
Series production scheduled for beginning (TSU, FIDS, PTM)
Purchasing process started for key components
Infrastructure work starting during YEST
Kicker platform in ECA5
WU created (to be uploaded)

9. SPS – ZS Ion traps Design of new ZS ion traps completed
Roger Barlow
Design of new ZS ion traps completed
Prototype validated with beam in ZSTF
Test on one LSS2 ZS during 2018 SPS run under consideration
Industrialisation process for external production ongoing.
Pre-series expected in Q
Production planned for 2018.
WU created (to be uploaded)
BC shared with SE section

10. SPS – TPSC4 Functional specification available
Steven Pavis
Functional specification available
Reuse of same solution as for TPS15 validated
Production in preparation
DIC in preparation
No integration issue
WU created (to be uploaded)
BC missing