1. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
Configuration of JEDEC standard plate with 15 components

2. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
The FE impact model of PCB with IC components potted by a resin

3. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
(a) Unpotted case; (b) single layer potting configuration sectional view with the cutting plane parallel to X-Z plane; (c) bilayer potting configuration sectional view with the cutting plane parallel to X-Z plane

4. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
The interconnection stress history for unpotted case

5. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
The effect of various potting materials on the averaged stress in interconnection along impact direction

6. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
History curves of interconnection stresses for four representative components: (a) U1, (b) U3, (c) U6, and (d) U8 as indicated in Fig. 1 with various potting materials

7. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
The maximum PCB central deflection for different potting materials

8. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
History curves of PCB deflection at center for different potting materials

9. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
Effect of bilayer potting thickness ratio on (a) averaged interconnection stress along z-axis, and (b) maximum PCB central deflection

10. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
Effect of varied exterior potting modulus of bilayer potting on (a) averaged interconnection stress along z-axis and (b) maximum PCB central deflection

11. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
Effect of varied interior potting modulus of bilayer potting on (a) averaged interconnection stress along z-axis, and (b) maximum PCB central deflection

12. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
Illustration of the simple analytical model for three configurations: unpotted, single layer potting design, and bilayer potting design

13. Date of download: 10/27/2017
Copyright © ASME. All rights reserved.
From: Effective Mitigation of Shock Loads in Embedded Electronic Packaging Using Bilayered Potting Materials
J. Electron. Packag. 2014;136(4): doi: /
Figure Legend:
(a) Contour plots of the normalized stress on the plane of the normalized moduli of the two potting layers, and (b) zoom-in plot. The unlabeled line indicates the same stress as the unpotted situation. The different dots mark the investigated potting cases in the simulations.