1. VLSI Design CMOS Inverter UNIT II :BASIC ELECTRICAL PROPERTIES
Sreenivasa Rao CH
Department of Electronics and Communication Engineering
VNR Vignana Jyothi Institute of Engineering and Technology
Hyderabad
Web:
VLSI Design
19/01/2009

2. Out Line
CMOS Inverter

3. Digital Gate Design Metrics:
Cost
Complexity and Area
Reliability and Robustness  Static Behavior
Noise Margin
Performance  Dynamic Behavior
Speed (Delay)
Energy Efficiency
Energy and Power Consumption, Energy-Delay

4. Noise Margins
Noise = unwanted variations in voltage which, if too great, can cause logic errors
Noise margin high (NMH): tolerable voltage range for which we interpret the inverter output as a logic 1
NMH = VOH – VIH
Noise margin low (NML): tolerable voltage range for which we interpret the inverter output as a logic 0
NML = VIL - VOL

5. Noise Margin (Cont)
(Source: Weste) 27

7. MOSFET MOSFET = “Metal-Oxide-Semiconductor Field-Effect Transistor”
Terminals:
G = gate
D = drain
S = source
B = body (substrate)

8. Biasing (NMOS) 2) (+) voltage on the gate
1) Source and substrate grounded (zero voltage)
2) (+) voltage on the gate
Attracts e-s to Si/SiO2 interface
When threshold voltage (VGS = VTn) is reached, an inversion layer is formed
3) (+) voltage on the drain
e-s in the channel drift from source to drain
current flows from drain to source

9. I-V Characteristics IDn vs. VGS: VTn = “threshold voltage”
Voltage where Si/SiO2 interface becomes strongly inverted with electrons
Voltage were NMOS transistor “turns on”

10. I-V Characteristics (cont.)
IDn vs. VDS:

11. Triode (Linear) Region
--vGS > Vt ,small vDS applied.
the channel conductance is proportional to vGS - Vt, and is proportional to (vGS - Vt) vDS.

12. where: mn = electron mobility in the channel,
Linear Region
IDn = f(VGS, VDS) and VDS < VGS – VTn, VGS ≥ VTn
Equation:
where: mn = electron mobility in the channel,
Cox = eox/tox, tox = oxide thickness, eox = oxide permittivity (3.9e0 for SiO2)

13. Saturation Region vGS > Vt.
--The induced channel acquires a tapered shape and its resistance increases as vDS is increased.

14. Saturation Region IDnsat = f(VGS) and VDS ≥ VGS – VTn, VGS ≥ VTn
Equation:

15. NFET Summary
Operating regions:
linear:
saturation:

16. P Channel device :Circuit Symbol

17. PMOS Cross-Section Appropriate I-V equations found by:
1) reversing the direction of ID
2) reversing the polarity of all bias voltages (VBS => VSB, VGS => VSG, VDS => VSD)

18. Biasing (PMOS) 1) Source and substrate grounded (zero voltage)
2) (-) voltage on the gate
Attracts h+s to Si/SiO2 interface
When threshold voltage (VSG = -VTp) is reached, an inversion layer is formed
3) (-) voltage on the drain
h+s in the channel drift from source to drain
current flows from source to drain

19. Why CMOS Inverter?
CMOS because it is the dominating technology of the era.
High Packing Density
Relatively Easy Process
Inverter because it is the nucleus of all digital designs.
Behavior of more intricate structures (logic gates, adders, etc.) can be almost completely derived by extrapolating the results obtained from the inverters.

20. CMOS means Complementary MOS:
CMOS INVERTER
CMOS means Complementary MOS:
NMOS and PMOS working together in a circuit
VDD (Logic 1) S D
VOUT D
VIN S

21. ANALYSIS OF INVERTER CIRCUIT: UNLOADED
VDD (Logic 1)
+ VGS(P) - S
Also note:
VGS(N) = VIN
VGS(P) = VIN - VDD
VOUT = VDS(N) D
VOUT D +
VDS(N) _
VIN
+ VGS(N) - S

22. CMOS Inverter: A First Glance
out C L DD
PMOS
NMOS
Driven by Output
Of another gate
=> Fanin
Collective Capacitances
Of Wires and Gates
=> Fanout

23. CMOS Inverter Characteristics
No current flow for either logical 1 or logical 0 inputs
Full logical 1 and 0 levels are presented at the output
For devices of similar dimensions the p – channel is slower than the n – channel device

24. CMOS Inverter Static BehaviorDD
Vin = VDD
out R n V DD
out R p
Vin = 0

25. CMOS Inverter Dynamic Behavior
VDD Rp
Vout CL
Vin = 0
Low to High
Vin = V DD CL
VDD
Vout Rn
High to Low
Charge
Discharge
For class.
response determined mainly by the output capacitance of the gate, CL - drain diffusion capacitance of the NMOS and PMOS transistors; the connecting wires, and the input capacitances of the fan-out gates
A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance or the transistor (or both)
Decreasing the on-resistance achieved by increasing the W/L ratio of the device
Be award that the on-resistance of the NMOS and PMOS transistors is not constant; rather it is a nonlinear function of the voltage across the transistor
Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn)

26. CMOS Properties (1) Full rail-to-rail swing Low output impedance
High noise margins
Logic levels not dependent upon the relative device sizes => Ratioless
Transistors can be minimum size
Low output impedance
Large Fan-out (albeit with degraded performance)
Typical output resistance in k range.
rail-to-rail - Vdd to 0V giving good noise margins
power dissipation - no path between Vdd and Gnd in steady state (ignores leakage current)
ratioless - logic levels are not dependent upon relative device sizes (as in NMOS), so transistors can be minimum size
single inverter can theoretically drive an infinite number of gates and still be functionally operational; fan-out increases propagation delay
steady state path to Vdd or Gnd - low output impedance, so less sensitive to noise

27. CMOS Properties (2)
Extremely high input resistance (MOS transistor is near perfect insulator)
nearly zero steady-state input current
No direct path between power and ground under steady-state (but there always exists a path with finite resistance between the output and either VDD or GND)
NO static power dissipation
Propagation delay a function of load capacitance and resistance of transistors

28. DC Voltage Transfer Characteristic
Ideal VTC of an INV
(Source: D. Hodges) 27

29. NMOS Short Channel I-V Plot
ID (A)
VDS (V)
X 10-4
VGS = 1.0 V
VGS = 1.5 V
VGS = 2.0 V
VGS = 2.5 V
Linear dependence
Ld is drawn length
Linear dependence of saturation current wrt VGS
Velocity saturation causes device to saturate for substantially smaller values of VDS.
Results in a substantial drop in current drive for high voltage levels.
Eg at VGS = 2.5V and VDS = 2.5V, the drain current of the short channel device is only 40% of the corresponding value of the long channel device (220 uA versus 540 uA)
NMOS transistor, 0.25 m, Ld = 0.25 m, W/L = 1.5, VDD = 2.5 V,
VT = 0.4 V

30. PMOS Short Channel I-V Plot
All polarities of all voltages and currents are reversed
ID (A)
VDS (V)
X 10-4
VGS = -1.0 V
VGS = -1.5 V
VGS = -2.0 V
VGS = -2.5 V
PMOS transistor, 0.25 m, Ld = 0.25 m, W/L = 1.5, VDD = 2.5 V,
VT = -0.4 V
All the derived equations hold for PMOS – for PMOS devices the polarities of all voltages and currents are reversed
Due to lower mobility, the maximum current is only 42% of what is achieved by a similar NMOS transistor
Effects of velocity saturation are less pronounced than in NMOS (smaller mobility of holes act electrons)

31. CMOS Inverter VTC Graphical Method
* VTC = Voltage-Transfer Characteristics
Graphical Method
(Source: Weste) 27

32. Transforming PMOS I-V Lines
Want common coordinate set Vin, Vout, and IDn
Vout
IDn
IDSp = -IDSn
VGSn = Vin ; VGSp = Vin - VDD
VDSn = Vout ; VDSp = Vout - VDD
VGSp = -2.5
VGSp = -1
Vin = 1.5
Vin = 0
Vin = 1.5
Vin = 0
Do inverter transistor schematic on the board labeling all sources, drains, and gates.
Mirror around x-axis
Vin = VDD + VGSp
IDn = -IDp
Horiz. shift over VDD
Vout = VDD + VDSp

33. CMOS Inverter Load Lines
PMOS
NMOS
X 10-4
Vin = 0V
Vin = 2.5V
Vin = 0.5V
Vin = 2.0V
IDn (A)
Vin = 1.0V
Vin = 1.5V
Vin = 1V
Vin = 1.5V
Vin = 2V
Vin = 0.5V
Vin = 1.0V
Vin = 1.5V
dc points located at the intersection of the corresponding load lines
Note all operating points are located either at the high or low output levels
Vin = 0.5V
Vin = 2.0V
Vin = 2.5V
Vin = 0V
Vout (V)
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V

34. CMOS Inverter VTC 27

35. CMOS Inverter VTC Vout (V) Vin (V) Vin = Vout A B C D E NMOS off
PMOS Lin
NMOS sat
PMOS Lin
Vin = Vout A B C
NMOS sat
PMOS sat
Vout (V) D
NMOS Lin
PMOS sat
NMOS Lin
PMOS off
For lecture
VTC of the inverter exhibits a very narrow transition zone; high gain during switching transient (when both PMOS and NMOS are simultaneously on and in saturation). In that region, a small change in input voltage results in a large output voltage variation.
Indicate on VTC plot where VTn and VTp lie E
Vin (V)

36. CMOS Inverter
Region (A) VIN < VTN NMOS off, PMOS on in Linear IDS = 0
Vout = VDD = VOH and VDSP = Vout – VDD = 0
Region (B) As VIN > VTN NMOS on in Sat since VDSN is still larger than VGS-VTN. PMOS is on in linear and current starts to flow from VDD to GND.
Region (C) As VIN increases more, both PMOS and NMOS enter Saturation mode. A large amount of current, IDD flows.
Region (D) VDD/2 < VIN < VDD - |VTP| NMOS changes to Linear mode while PMOS is still in Sat. The amount of current is reduced
Region (E) As VIN > Vdd - |VTP|, PMOS cut off no current flows. NMOS is in Linear mode connecting output to GND therefore VOUT = GND = VOL 27

37. CMOS Inverter
(Source: Weste) 27

38. CMOS INVERTER: REGION AID
VGS(N) < VTH(N)
VDS(P) = VGS(P) - VTH(P)
VGS(P) < VTH(N) - VDD
No current flow in Region A!
NMOS cutoff mode
PMOS triode mode
VDS
VDD

39. CMOS INVERTER: REGION BID
VGS(N) = VTH(N) + e
VDS(P) = VGS(P) - VTH(P)
VGS(P) = VTH(N) + e - VDD
NMOS saturation mode
PMOS triode mode
VDS(N) = VGS(N) - VTH(N)
VDS
VDD

40. CMOS INVERTER: REGION CID
NMOS saturation mode
PMOS saturation mode
VDS(P) = VGS(P) - VTH(P)
VDS(N) = VGS(N) - VTH(N)
VDS
VDD

41. CMOS INVERTER: REGION DID
VGS(N) = VDD + VTH(P) - e
VGS(P) = VTH(P) - e
VDS(N) = VGS(N) - VTH(N)
NMOS triode mode
PMOS saturation mode
VDS(P) = VGS(P) - VTH(P)
VDS
VDD

42. CMOS INVERTER: REGION E
VGS(N) > VTH(P) + VDD ID
VDS(N) = VGS(N) - VTH(N)
VGS(P) > VTH(P)
No current flow in Region E!
NMOS triode mode
PMOS cutoff mode
VDS
VDD

43. CMOS INVERTER RESPONSE: CURRENT FLOWID
VIN D A B C E
VDD

44. CMOS INVERTER RESPONSE
VOUT
VDD
VM: Voltage when
VIN = VOUT (= VM)
VIN D A B C E
VDD

45. Voltage transfer characteristic of the CMOS inverter.

46. CMOS Inverter: RC Delay
Step Input
Vin = VDD
Vin = GND 27

47. CMOS Inverter: RC Delay
tPHL ≈ 0.69RNCL
tPLH ≈ 0.69RPCL 27

48. Robustness of CMOS Inverter
Precise Values of Switching Threshold, VM
VM is defined as the point where Vin = Vout
Noise Margins
Piece-Wise Linear Approximation
Maximization
Process Variations
Device Variations
Technology Scaling

49. Complimentary Transistor Pull – Up (CMOS)
Vdd
Vout
Vtn
Vtp
P on
N off
N on
P off Vo
Vin
Both On
Vin
Vss
Vdd
Vss
Logic 0
Logic 1

50. Vout
Vtn
Vtp
1: Logic 0 : p on ; n off
5: Logic 1: p off ; n on
2: Vin > Vtn.
Vdsn large – n in saturation
Vdsp small – p in resistive
Small current from Vdd to Vss
4: same as 2 except reversed p and n
3: Both transistors are in saturation
Large instantaneous current flows
P on
N off
N on
P off
Both On
Vin
Vss
Vdd 1 2 3 4 5

51. CMOS INVERTER CHARACTERISTICS
Current through n-channel pull-down transistor
Current through p-channel pull-up transistor
If n = p and Vtp = –Vtn
At logic threshold, In = Ip
Mobilities are unequal : µn = 2.5 µp
Z = L/W
Zpu/Zpd = 2.5:1 for a symmetrical CMOS inverter

52. References
Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian Dougles and A. Pucknell,
Digital Integrated Circuits - John M. Rabaey, PHI,
CMOS VLSI design, Neil H.E.Weste,David Harris,Ayan Banerjee

53. ---In science, self –satisfaction is death
---In science, self –satisfaction is death. Personal satisfaction is death of scientist. Collective self satisfaction is death of research.
It is restless, anxiety ,dissatisfaction, agony of mind that nourish science……..
Jacques Lucien Monod