1. The SOI Issue – Material for PXD9
VXD Workshop, Wetzlar, February 2013
Ladislav Andricek, MPI für Physik, HLL

2. SOI production – a reminder
Raw wafer supply  pre-processing  SOI  DEPFET process  thinning, dicing, mounting..
Key Process Modules for (thick) SOI production:
1/ Wafer bonding  Somewhat special due to our implanted back side
2/ Edge treatment of the top wafer
3/ grinding and polishing
Standard for SOI Wafer production
525 µm
Belle II PXD-SVD Workshop, Vienna, Feb. 2012
Ladislav Andricek, MPI für Physik, HLL

3. Challenges – wafer bonding
Initial problems with wafer bonding (Icemos, VTT, EVG, ShinEtsu)
solved with pre-treatment before bonding
cleaning, annealing of oxide after implant (re-crystallization)
status for 1st PXD batch (Icemos and SEH): Zero voids!
VXD Workshop, Wetzlar, February 2013
Ladislav Andricek, MPI für Physik, HLL

4. Challenges – edge treatment
Icemos
SEH
Icemos
status for 1st PXD batch (Icemos and SEH): “perfect”
VXD Workshop, Wetzlar, February 2013
Ladislav Andricek, MPI für Physik, HLL

5. SOI for the 2nd batch – the set-back
28 Wafers produced at Icemos: same process as first batch!!
24 Wafers at ShinEtsu
 voids, ~ few mm size, at the rim of the wafer
IR pic, SHE
Siemens CT
SAM picture from IceMos
Icemos: all wafers affected, ~20 voids/wafer
ShinEtsu: almost all wafers aff., 1-4 voids/wafer
VXD Workshop, Wetzlar, February 2013
Ladislav Andricek, MPI für Physik, HLL

6. Why???? Void-free IceMos wafer
issue at both SOI manufacturers
most likely the problem is the pre-processing (implant, litho..) at HLL
Icemos agreed to do another run with left-overs from 2nd batch and the last pre-processed top wafers from HLL
17 wafers with improved cleaning step at HLL sent to Icemos for SOI
Icemos split the batch into three with different re-crystallization temperatures
processing was done free of charge
Result: all 17 wafers completely void free prime grade SOI!!
Conclusion:
reason for voids are residues from pre-processing
better cleaning at HLL solves the problem
voids are probably filled with organic contaminations under low pressure
Wafer inventory as of today:
24 Wafers from SEH with a few voids at the rim
17 wafers from IceMos void free
Decision
voids are only at the rim, no active structures there, no etching
Risk for process issues considered to be small
need 18 wafers for 2nd PXD batch
Start 2nd batch PXD with at least 18 SEH SOI wafers
Void-free IceMos wafer
VXD Workshop, Wetzlar, February 2013
Ladislav Andricek, MPI für Physik, HLL

7. Compare IceMos – SEH Thickness 450µm/75µm for both
Bow and warp: ~70 µm SEH and ~40µm for Icemos
different post-bond anneal temperatures (TSEH<TICE)
Test diodes produced on both types of wafers are very good
IceMos diodes, 0.25 cm²
SEH diodes, 0.25 cm²
VXD Workshop, Wetzlar, February 2013
Ladislav Andricek, MPI für Physik, HLL

8. Compare IceMos – SEH
small difference in full depletion voltage and effective thickness
because of larger out-diffusion of buried implant at IceMos???
IceMos diodes, 0.25 cm²
Vfd= 38 V
teff= 66 µm
SEH diodes, 0.25 cm²
Vfd= 44 V
teff= 71 µm
VXD Workshop, Wetzlar, February 2013
Ladislav Andricek, MPI für Physik, HLL

9. In Summary
We have enough (almost) prime grade SOI wafers and we can continue with PXD batch 2 ….
and we have a lot of (prime grade) SOI for dummies  ….
VXD Workshop, Wetzlar, February 2013
Ladislav Andricek, MPI für Physik, HLL