1. Ivan Perić University of Heidelberg Germany
DCD4_Pipeline
Ivan Perić
University of Heidelberg
Germany

2. DCDB4_Pipeline Features: Pipeline ADC (designed sampling rate ~ 50ns)
New digital block (designed for up to 640MHz, low power serializers)
Analog common mode correction (can be switched)
Temperature stabile reference
High precision calibration DAC
The measurement results on single chips are good

3. DCDBPip
TIA
ADC
200 µm
5 mm

4. Pipelined vs. Cyclic ADC
Algorithm:
Copy here copy there
Compare with threshold add reference
Subtract two outputs (duplicate)
Pipeline ADC
Memory cell
ADC1
ADC2
MSB cell
LSB cells 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Hi Lo
Cyclic ADC approach
- Algorithm performed cyclically (ping pong wise)
by two memory cell pairs
- Two ADCs per channel
- 200ns sampling rate/ADC
- ADC clocked with 100MHz
- Pipeline ADC approach
- Algorithm performed as in production line by 8 memory cell pairs
- One ADC per channel
- 100ns sampling rate when clocked with 50MHz
- Designed for 50 ns sampling rate

5. DCDB4_Pipeline Measurement results on 4.1. module
3 Columns are measured
6 and 7 are ok
1 – LSB does not work (wire bond problem)
Column 2 – one of the significant bits does not work (wire bond problem)

6. DCDB4_Pipeline at 320MHz – new settings
Measurements done at 320MHz
Settings:
On the generators:
VDDA: 2.15V (364mA)
GNDA: 0V
VDDD: 2.0V (176mA)
GNDD: 0V
AMPLOW: 1.7V (247mA)
REFIN: 1.05V (50mA)
Measured on sense lines:
VDDA: 1.86V
GNDA: 0.14V
VDDD: 1.864V
GNDD: 0.077V
AMPLOW: 0.485V
REFIN: 1.0
Power consumption ~ 1.33mW
Bias currents for DCDRO: 0.28mA (LVDSin) and 5.45mA (LVDSout)

7. Test all ADCs – fit (-100 to 125)…

8. Test all ADCs – fit (-100 to 125)…
ADC gain 72nA/LSB gq 650pA/e)
Noise: ~0.55LSB gq 650pA/e)
220e
275e

9. Test one ADC – fit (-100 to 125) …

10. DCDB4_Pipeline at 320MHz VDDA varied +/- 50mV and AMPLOW +/- 50mA
No influence on the chip

11. DCDB4_Pipeline 3 out of four columns tested Noise ~40nA@320MHz
A few channels sensitive – they show missing codes around values -64 or 64
The problem is old, it exists since DCD1, now it has been understood – poor matching of transistors, the fix is to increase the setting VPSuorce with respect to VPFB and VPSource2 (good values for Sc., FB, Sc2.: 80, 70, 70)
VDDA, AMPLOW do not influence the behavior significantly
REFIN should be correct within +/- 50mV
Analog CMC tested and works
Band-Gap reference works
Current consumption at 320MHz:
VDDA: 364mA+AMPLOW (DCDB3 286mA+AMPLOW) (change +78mA)
AMPLOW: 247mA (DCDB3 182 mA) (change +65mA)
VDDD: 176mA (DCDB3 268mA) (change -92mA)
Total change: +51mA
DCDB4 tested even at 500MHz clock rate (64ns sampling time) and works