1. 9S12C Multiplexed Bus Expansion
Module 2.B
9S12C Multiplexed Bus Expansion
Tim Rogers 2017

2. A+B are the most complex interface we will study in 362
Learning Outcome #2
“An ability to interface a microcontroller to various devices”
A+B are the most complex interface we will study in 362
Bus Timing Analysis
9S12C Multiplexed Bus Expansion
General-Purpose I/O Ports
Buffered I/O Handling
Interrupt Handling
Buffered, Interrupt-Driven Printer Design Example
How?

3. Some Introduction
Internal visibility:
We can see what is happening on the internal bus as well as the external one
Single Chip Mode (just use internal SRAM). Expanded Mode (Can hook up external SRAM and turn on “internal visibility”)
The expanded data bus can be 8-bits (“narrow mode”) or 16- bits (“wide mode”)
Signals of interest include the following:
Port A – high byte of address/data (wide mode) or high byte of address/8-bit data (narrow mode)
Port B – low byte of address/data (wide mode)
Port E – bus control signals
E – bus clock (used to de-multiplex the address and data)
R/W’ – read/write enable
LSTRB’ – low byte strobe (used to distinguish word writes from byte writes in “wide” mode)
By Default: 9S12 is Normal Single Chip Mode (no signals visible)
For HW 5 Q 3 and 4:
Normal Expanded Narrow Mode used.
With internal visibility turned on.
For Lab 5:
Normal Expanded Wide Mode used.
With internal visibility turned on.

4. High-level Picture of External Memory
2.B
2.A
Only one bus for Address and Data
Bus is “Multiplexed”:
1st half of clock cycle: do address
2nd half of clock cycle: send data
Address Latch +
Address Decode PLD
CPU
External
Memory Chip
Chip Enable (CE)
16-bits /
Data/Address Bus
Address (in)
8-bits /
Data (in/out)
R/W’
Output Enable (OE)
CLK
Write Enable (WE)

5. Figure 1 of AN2408

6. Schematic Based on PLD
Note: Schematic is based on pin assignments generated automatically by the fitter for this PLD.

7. Interface Logic ABEL source file available on Homework page
MODULE mem9s12c
TITLE '9S12C Memory Interface'
DECLARATIONS
PA0..PA7 pin; " MCU Port A
ECLK pin; " MCU E-clock
RW pin; " MCU Read/Write
!CS, !OE, !WE pin istype 'com';
LA8..LA15 pin istype 'reg_D'; " demultiplexed address
EQUATIONS
[LA8..LA15].D = [PA0..PA7];
[LA8..LA15].CLK = ECLK;
CS = !LA15.Q & ECLK; " map SRAM into lower half of address space
OE = RW & ECLK;
WE = !RW & ECLK;
END
Port A will be used for data on 2nd half of clock cycle.
Latch it on the 1st half.
Same logic for OE and WE that we saw in simple examples
CS = CE:
Only asserted when uppermost bit is 0.

8. Fitter Report (Summary)

9. Critical Path Analysis: OE and WE
These are the combinational output delay paths (pertinent for OE and WE).

10. Critical Path Analysis: Latched Address
These are the clock edge to latched output delay paths (where ECLK provides the clock edge). Note that the latched (de-multiplexed) address bus is valid 4 ns following the low-to-high ECLK transition; the CS signal, which here is dependent on LA15 and being gated with ECLK, is valid 7.5 ns following the low-to-high ECLK transition.

11. 9S12C Bus Signals
Note: These signals are not available on the 9S12C32

12. 9S12C A.C. Specifications (Sample)

13. This figure combines what happens read and write diagrams
9S12C General External Bus Timing
This figure combines what happens read and write diagrams
Bus on Read
Bus on Write

14. 9S12C General External Bus Timing

15. 9S12C General External Bus Timing

16. 9S12C General External Bus Timing

17. 9S12C A.C. Specifications (Sample)

18. 9S12C General External Bus Timing
tCY

19. 9S12C A.C. Specifications (Sample)

20. 9S12C General External Bus Timing
tCY
tAD

21. 9S12C A.C. Specifications (Sample)

22. 9S12C General External Bus Timing
tCY
tAD
tMAH

23. 9S12C A.C. Specifications (Sample)

24. 9S12C General External Bus Timing
tCY
tDSR
tAD
tDHR
tMAH

25. 9S12C A.C. Specifications (Sample)

26. 9S12C General External Bus Timing
tCY
tDSR
tAD
tDHR
tMAH
tDDW

27. 9S12C A.C. Specifications (Sample)

28. 9S12C General External Bus Timing
tCY
tDSR
tAD
tDHR
tMAH
tDHW
tDDW

29. 9S12C A.C. Specifications (Sample)

30. “input setup” time (tIS) available on write
9S12C General External Bus Timing
tCY
tDSR
tAD
tDHR
tMAH
tDSW
tDHW
tDDW
“input setup” time (tIS) available on write

31. 9S12C A.C. Specifications (Sample)

32. “input setup” time (tIS) available on write
9S12C General External Bus Timing
tCY
tDSR
tACCA
tAD
tDHR
tMAH
tDSW
tDHW
tDDW
“input setup” time (tIS) available on write
“address access” time (tAA) available on read

33. 9S12C A.C. Specifications (Sample)

34. “input setup” time (tIS) available on write
9S12C General External Bus Timing
tCY
tDSR
tACCA
tAD
tDHR
tMAH
tDSW
tDHW
tDDW
tRWD
Note: tRWD != tAD
For expanded bus
“input setup” time (tIS) available on write
“address access” time (tAA) available on read

35. 9S12C A.C. Specifications (Sample)

36. “input setup” time (tIS) available on write
9S12C General External Bus Timing
tCY
tDSR
tACCA
tAD
tDHR
tMAH
tDSW
tDHW
tDDW
tRWD
tRWH
“input setup” time (tIS) available on write
“address access” time (tAA) available on read

37. 9S12C CPU Read/Write Timing Diagram
tCYC = 40 ns

38. 9S12C CPU Read/Write Timing Diagram

39. 9S12C CPU Read/Write Timing Diagram

40. 9S12C CPU Read/Write Timing Diagram

41. 9S12C CPU Read/Write Timing Diagram
Spoiler alert – this is the solution to problem 2 on homework 5

42. MSO Display for Experiment 5 Demo Code
ECLK
R/W
LSTRB
PB0
LA15-LA0   
PA0-7
PB0-7

43. Potential Design Question
Given:
9S12 operating with/without stretch
A specific PLD you can get timings for + abel file with associated with with logic
A specific SRAM part with the data sheet
Determine:
Does this setup violate setup/hold times
What is the read margin
What is the maximum clock rate you can sustain and still achieve 10% margin.
When calculating margin as a percent, it is a percent of what?
The SRAM timing parameter that is determining the critical path

44. Example Timing Diagram

45. 9S12 Configurable Memory Map
Out of reset, SRAM is mapped to 800-FFF
Out of reset, Flash is mapped to 8000-FFFF

46. Configuration Registers
9212 CPU registers are A, B, D, SP, PC, X and Y
THESE HAVE NOTHING TO DO WITH THE CONFIGURATION REGISTERS
There when we use the microcontroller there is a lot of setup/initialization of the CPU/Peripherals/Pins etc…
We control these via “memory mapped registers” or “configuration registers”
A portion of the address space is devoted to these registers and when you write to these locations the value doesn’t actually go to memory is goes to a configuration register

47. 9S12 Configurable Memory Map
This is the space devoted to configuration registers
To maximize space, configuration is often done on a bit-by-bit basis.

48. Our first (of many) configuration registers
INITRM Register (initializes SRAM position in memory)
INITRM Register (8-bits)
Memory location: $11
Bits 7-3 named:
RAM15-RAM11
So by default - SRAM mapped to:
b to b or
$800 to $FFF
Recall: only 2k (11-bits) worth of internal SRAM on the 9S12
These bits specify the upper 5 bits of the SRAM address.
Out of reset these bits are 00001b

49. Can use other confirmation registers to remap all regions
If conflicts occur, the following precedence applies:
register space
internal SRAM
byte-erasable EEPROM (not on 9S12C32)
flash
external memory