1. TDC per 4 pixels – End of Column Approach
Sakari Tiuraniemi - CERN

2. TDC per 4 pixels – EOC RX 45 LVDS 11 Ref CLK 312.5 MHz
Digital processing
32-bit
DLL
TDC bank
address RX 4
serialize

3. TDC per 4 pixels – EOC 1 2 3 4 5 6 7 8 9 10 11 12 . 23 24 34 35 45
TDC 1
TDC 2
TDC 10
TDC 11
address
11 TDCs per column – 2x32-bit hit registers each
11 transmission lines per column
Each shared with 4 pixels (except the first one shared with 5)
Solves the clustering problem
NBmax = 64
32 bits used to leave some extra space (64 read out lines would fill the full space)
Address encoding
4 groups of 11 pixels
11 TDCs with 4 pixels

4. TDC per 4 pixels – EOC 0.2 um 280 um 140 um M5 M6
11x2 Hit Registers per column
22 in parallel
Width of hit register 5.72 um < 150 um in total
Number of bits limited by number of readout lines:
X = NBxNREGxW
X = 300 um (width of pixel)
W = 0.2 um (2 metal layers; M5 and M6)
NREG= 11x2
NB = number of bits
NB < 300um / (11x2x0.2um) = 68.18
NBmax = 64
TCLK = 6.4 ns
FCLK = MHz
NBmax = 64 (4px per TDC)
FCLK = MHz, TCLK = 6.4 ns
NB = 32
FCLK = MHz, TCLK = 3.2 ns

5. TDC per 4 pixels – EOC In total 440 TDCs
DLL
from other pixels of the column
to next column
In total 440 TDCs
880 Hit Register
D-flip-flops
~ 10 times more hit registers, but:
4 times less DFFs per register and
2 times smaller DFFs (~ 2 times less power consumption)
Needs simulation
Also DLL consumes less power: ~7 mWavg

6. Start&Stop Generation
TDC per 4 pixels – End of Column (11 TDCs per Column, 32 bits)
Pixel
Start&Stop Generation 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
DLL:
Hit px 1
Hit Register 2
Hit Register 1
leading edge trigger
trailing edge trigger

7. Digital Post-Processing32 E N C 2 1
7 - bit
Coarse
CTR
Hit - leading
edge
Hit – trailing 5 7 R G 12 S BF τ
312.5 MHz
Enable1
Ref CLK
Reset
Enable2

8. Digital Post-Processing
Two 5-bit encoders followed by two 12-bit registers to store both hit (5 bits) and coarse times (7 bits)
To make sure coarse time is correct, it is stored at both leading and trailing edge
Is 7 bits enough for the coarse now that the clock cycle is 3.2ns?
2 x 12 - bits per hit are serialized and transmitted out of the chip
Shift registers will be used at this stage to bring the data off chip
The readout of the hit registers to the post digital processing needs to be looked into more closely
11 x 2 x 32-bits

9. The End