1. Magnitude Comparator
Module M5.2
Section 6.1

2. 4-Bit Equality Detector
A_EQ_B
B[3..0]

3. Magnitude Comparator A_LT_B A[3..0] Magnitude Detector A_EQ_B B[3..0]
A_GT_B

4. Magnitude Comparator How can we find A_GT_B?
How many rows would a truth table have?
28 = 256!

5. Magnitude Comparator Find A_GT_B Because A3 > B3 i.e. A3 & !B3 = 1
If A = 1001 and
B = 0111
is A > B?
Why?
Therefore, one term in the
logic equation for A_GT_B is
A3 & !B3

6. Magnitude Comparator A_GT_B = A3 & !B3 # ….. Because A3 = B3 and
# …..
Because A3 = B3 and
A2 > B2
i.e. C3 = 1 and
A2 & !B2 = 1
If A = 1101 and
B = 1011
is A > B?
Why?
Therefore, the next term in the
logic equation for A_GT_B is
C3 & A2 & !B2

7. Magnitude Comparator A_GT_B = A3 & !B3 # C3 & A2 & !B2 # …..
# …..
Because A3 = B3 and
A2 = B2 and
A1 > B1
i.e. C3 = 1 and C2 = 1 and
A1 & !B1 = 1
If A = 1010 and
B = 1001
is A > B?
Why?
Therefore, the next term in the
logic equation for A_GT_B is
C3 & C2 & A1 & !B1

8. Magnitude Comparator A_GT_B = A3 & !B3 # C3 & A2 & !B2
# C3 & C2 & A1 & !B1
# …..
Because A3 = B3 and
A2 = B2 and
A1 = B1 and
A0 > B0
i.e. C3 = 1 and C2 = 1 and
C1 = 1 and A0 & !B0 = 1
If A = 1011 and
B = 1010
is A > B?
Why?
Therefore, the last term in the
logic equation for A_GT_B is
C3 & C2 & C1 & A0 & !B0

9. Magnitude Comparator A_GT_B = A3 & !B3 # C3 & A2 & !B2
# C3 & C2 & A1 & !B1
# C3 & C2 & C1 & A0 & !B0

10. Magnitude Comparator Find A_LT_B A_LT_B = !A3 & B3 # C3 & !A2 & B2
# C3 & C2 & !A1 & B1
# C3 & C2 & C1 & !A0 & B0

11. ABEL Program MODULE magcomp4
TITLE '4-BIT COMPARATOR, R. Haskell, 9/21/02‘
DECLARATIONS
" INPUT PINS "
A3..A0 PIN 6,7, 11, 5;
A = [A3..A0];
B3..B0 PIN 72, 71, 66, 70;
B = [B3..B0];
" OUTPUT PINS "
A_EQ_B PIN 36;
A_LT_B PIN 37;
A_GT_B PIN 35;
C3..C0 NODE;
C = [C3..C0];

12. ABEL Program (cont.) EQUATIONS C = !(A $ B);
A_EQ_B = C0 & C1 & C2 & C3;
A_GT_B = A3 & !B3
# C3 & A2 & !B2
# C3 & C2 & A1 & !B1
# C3 & C2 & C1 & A0 & !B0;
A_LT_B = !A3 & B3
# C3 & !A2 & B2
# C3 & C2 & !A1 & B1
# C3 & C2 & C1 & !A0 & B0;

13. ABEL Program (cont.)
test_vectors ([A, B] -> [A_EQ_B, A_LT_B, A_GT_B])
[0, 0] -> [1, 0, 0];
[2, 5] -> [0, 1, 0];
[10, 12] -> [0, 1, 0];
[7, 8] -> [0, 1, 0];
[4, 2] -> [0, 0, 1];
[6, 6] -> [1, 0, 0];
[1, 7] -> [0, 1, 0];
[5, 13] -> [0, 1, 0];
[12, 0] -> [0, 0, 1];
[6, 3] -> [0, 0, 1];
[9, 9] -> [1, 0, 0];
[12, 13] -> [0, 1, 0];
[7, 0] -> [0, 0, 1];
[4, 1] -> [0, 0, 1];
[3, 2] -> [0, 0, 1];
[15, 15] -> [1, 0, 0];
END

17. TTL Comparators 1 2 3 4 5 6 7 9 10 11 12 8 19 20 17 18 15 16 13 14
GND
Vcc
P>Q P0 Q0 P1 Q1 P2 Q2 P3 Q3
P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4
74LS682 B3
A<Bin
A=Bin
A>Bin
A>Bout
A=Bout
A<Bout A3 B2 A2 A1 B1 A0 B0
74LS85

18. Cascading two 74LS85s

19. Question Draw a logic circuit for what is in the green box. P_GT_Q
P_EQ_Q
P_LT_Q 1 2 3 4 5 6 7 9 10 11 12 8 19 20 17 18 15 16 13 14
GND
Vcc
P>Q P0 Q0 P1 Q1 P2 Q2 P3 Q3
P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4
74LS682
Draw a logic circuit for
what is in the green box.