1. Dave Lim and John Lockwood Washington University,
Simulation of the Hello World Application for the Field-programmable Port Extender (FPX)
Dave Lim and John Lockwood
Washington University,
Applied Research Lab
Fall 2001 Gigabit Kits Workshop
Supported by NSF-ANI and Xilinx Corp

2. Problem Statement General Statement Details
“Implement a plug-in module that monitors a traffic flow. For cells with payloads that begin with “Hello”, have the module replace the following bytes with “World”.
Details
Scan Flows on VCI=5
Match the content of the cell for the “HELLO”
ASCII: “HELLO”
Hex: 48 – 45 – 4C – 4C – 4F
Binary: 0100, , , , ,1111
Replace following contents with “WORLD.”
ASCII “WORLD.”
Hex: 57 – 4F – 52 – 4C – 44 – 2E
Binary: 0101,0111 – 0100,1111 – 0101,0010 – 0100,1100 – 0100,0100 – 0010,1110

3. “Hello, World” Module Function

4. Case 1: Mismatched VCI Only process Cells on the selected VCI
All other flows should pass unchanged

5. Case 2: Mismatched Source String
Cell payload must contain “HELLO” in payload.
“MELLO”  “HELLO”

6. Case 3: Mismatched Source String [word 2]
Payload must match over entire string.
Data arrives as streaming words

7. Hello World Block Diagram
tcaff_sw_rad
tcaff_sw_nid
soc_sw_nid
soc_sw_rad
d_sw_nid
O_WO
d_sw_rad
RLD
NUL
data_sel
cnt_en
data_in
cntr_output
hellofsm
counter_4_bit
soc_in
ld_cntr
cntr_output
init_cntr_val
rst_cntr
data_sel
clk
reset
clk
reset

8. Finite State Machine Bubble Diagram
SOC=“1”
VCI=5
Data_in=“HELL”
Init
Pad
Hell_check
O_check
SOC=“1”
VCI/=5
SOC=“1”
cnt=“1101”
Data_in/=“HELL”
Data_in/=“O”
SOC=“0”
cnt=“1101”
Dout
Wo_rld
Data_in=“O”

9. Module Implementation
D_MOD_IN[31:0]
D_MOD_OUT[31:0]
Data
Interface
SOC_MOD_IN
SOC_MOD_OUT
TCA_MOD_OUT
TCA_MOD_IN
Module
Logic X
SRAM_GR
SRAM_REQ
SRAM_D_IN[35:0]
SRAM
Interface
SRAM_D_OUT[35:0]
SRAM_ADDR[17:0]
SRAM_RW X
SDRAM_GR
SDRAM_REQ
SDRAM_DATA[63:0]
SDRAM_DATA[63:0]
SDRAM
Interface
SRAM_ADDR[17:0]
SRAM_RW
CLK
Module
Interface
RESET_L
ENABLE_L
READY_L

10. Hello, World Entity
RAD
RAD_Loopback_Core

11. TestBench configuration
INPUT_CELLS.DAT
rad_loopback
Fake_NID
soc
Data
tcaff
rad_loopback_core
NID_Out
HelloWorld_module
NID_In
loopback_module
CELLSOUT.DAT
soc
Data
tcaff

12. Download Files Visit Download HelloWorld Testbench
Download HelloWorld Testbench
Right-click on Hello.tar
Save Target in: h:\
Access Files in Cygwin Bash Shell
Start > Engineering > FPGA Tools > Cygwin Bash Shell
cd /cygdrive/h/
gunzip Hello.tar.gz
tar xvf Hello.tar
cd HelloFiles ls
shows three folders: ./sim, ./syn, ./vhdl

13. Manifest of Files in Hello.tar
Contains:
Makefile: Build and complile programs
INPUT_CELLS.DAT: Cells written into simulation (Hex)
modelsim.ini: Sets path for libraries needed for compiling and simulating
testbench.vhd: Testbench for RAD
fake_NID_in.vhd: Utilities to save cells to file
fake_NID_out.vhd: Utility to read cells from file
clock.vhd: Utility to read cells from file
rad_loopback.vhd: Top-level design
rad_loopback_core.vhd: Core that instantiates helloworld_module
loopback_module.vhd: Module that passes data through unchanged
blink.vhd: Blinks LED when RAD module is downloaded onto FPX
helloworld_module.vhd: Top-level helloworld design
hellofsm.vhd: Hellworld finite state machine
counter_4_bit.vhd: Counter that counts number of words received
mux4vhd: Multiplexor for selecting outputs
data_flop.vhd: Output flop for data
soc_flop.vhd: Output flop for SOC signal
tca_flop.vhd: Output flop for TCA signal
rad_loopback.ucf: Pin mapping for RAD FPGA
bitgen.ut: Options file for generating .bit file
build: Script file for creating the backend

14. Source: Multiplexor (from mux4.vhd)
entity mux4 is
port (a, b, c, d : in std_logic_vector(31 downto 0);
sel : in std_logic_vector(1 downto 0);
output : out std_logic_vector(31 downto 0));
end mux4;
architecture behavioral of mux4 is
begin
mux_process: process (sel,a,b,c,d)
case sel is
when "00" => output <= a;
when "01" => output <= b;
when "10" => output <= c;
when "11" => output <= d;
when others => output <= a;
end case;
end process mux_process;
end behavioral;

15. Source: State transitions (from hellofsm.vhd)
state_trans:process(state,soc_in,cntr,data_in)
begin
case state is
when init => if (soc_in='1') then
if (data_in(19 downto 4)=x"0005") then
nxt_state <= pad;
else
nxt_state <= dout;
end if;
nxt_state <= init;
when pad => nxt_state <= hell_check;
when hell_check => if (data_in=x"48454c4c") then
nxt_state <= o_check;
when o_check => if (data_in(31 downto 24)=x"4f") then …

16. Source: Next State Assignments (from hellofsm.vhd)
clkd:process(clk)
begin
if (clk'event and clk='1') then
if (reset='0')then
state <= init;
else
state <= nxt_state;
end if;
end process clkd;

17. Contents of TESTCELL.DAT (1st Cell)
new_cell Indicates new cell
VCI=5 E
48454C4C 1st Payload word = “HELL”
4F nd Payload word = “O”

18. Contents of TESTCELL.DAT (2nd Cell)
new_cell Indicates new cell
VCI = 4
48454C4C 1st Payload word = “HELL”
4F nd Payload word = “O”

19. Simulation (Makefile)
go into sim directory
cd sim
type “make newsim”
Create a work directory to compile all the VHD designs into
type “make compile”
Compile all VHD designs
type “make sim”
Simulate top-level design using modelsim

20. Viewing Signals in Modelsim
type “view structure”
opens a window that allows you to view the overall design structure in a hierarchical fashion
type “view signals”
opens a window that allows you to pick out signal waveform that you want to look at during simulation
type “view wave”
opens a window for waveforms
type “add wave -r /*”
add all the waveforms in design
from signals window, [View menu] > signals > selected signals
add individual signals
Run simulation
type “run 1000”

21. Synthesis (Start Synplicity)
click Start > Engineering > FPGA Tools > Synplify Pro
Open project in Synplicity
click Open Project… > New Project...

22. Synthesis (Save project and add files)
File > Save
save project under h:\hellofiles\syn\
Add VHDL files
click Add File..
go to HelloFiles\vhdl\
highlight all .vhd files
click <-Add
click OK
Make sure VHDL files are in correct order
make sure that rad_loopback.vhd is last module; helloworld_module.vhd and rad_loopback_core.vhd are just above it

23. Synthesis (Set Implementation Options and Run)
click Impl Options…
Under Device
Technology: Xilinx Virtex-E
Part: XCV1000E
Speed: -7
Package: FG680
Under Options/Constraints
Frequency(Mhz): 100
Implementation Results
Implementation Name: rad-xcve1000
Results Directory: h:\hellofiles\syn\rad_xcve1000 (if this gives you a warning, click ‘yes’)
click Run
save project

24. Synthesis (running the backend script)
Try running backend script
Go to /cygrdrive/h/HelloFiles/syn/rad-xcve1000
type “./build”
Set path for Xilinx backend tools
go to fpx workshop webpage
under Synthesis for the 1pm session click on “cyg vars”
copy and paste the commands into cygwin
Run backend script again

25. Synthesis (backend script)
part=xcv1000e-7-fg680
design=rad_loopback
#ngdbuild - builds all the components into a ngd file
ngdbuild -p ${part} ${design} -uc ${design}.ucf
#ngd2vhdl - builds a post-synthesis vhdl file for simulation
ngd2vhdl -w ${design}.ngd ${design}_sim.vhd
#map - the logic components into xilinx specific logic gates
map -p ${part} -o top.ncd ${design}.ngd ${design}.pcf
#par - place and route the logic gates in the chip
par -w -ol 2 top.ncd ${design}.ncd ${design}.pcf
#bitgen - generates the bitstream
bitgen ${design}.ncd -b -l -w -f bitgen.ut

26. Exercise
Change VHDL code so that it says “HELLO GIGA BIT KITS WORK SHOP.” instead of “HELLO WORLD”.
Changes need to be done to hellofsm.vhd, mux.vhd and helloworld_module.vhd

27. New Bubble Diagram Init Pad Hell_check O_check Giga1 Wo_rld Dout Shop1
SOC=“1”
VCI=5
Data_in=“HELL”
Init
Pad
Hell_check
O_check
SOC=“1”
cnt=“1101”
Data_in/=“HELL”
Data_in=“O”
Data_in/=“O”
SOC=“1”
VCI/=5
Giga1
Wo_rld
Dout
SOC=“0”
cnt=“1101”
Shop1
Work
Giga2
Shop2
Kits
Bit

28. Sample Cell

29. Hex / ASCII Table [See your Handout!]
"Hex.txt" 34 lines, 1776 characters
Hx Symbol (Function) Hx Char Hx Char Hx Char
00 NUL (null) SPACE `
01 SOH (start of head) ! A a
02 STX (start of text) " B b
03 ETX (end of text) # C c
04 EOT (end of trans) $ D d
05 ENQ (enquiry) % E e
06 ACK (acknowledge) & F f
07 BEL (bell) ' G g
08 BS (backspace) ( H h
09 TAB (horizontal tab) 29 ) I i
0A LF (line feed) A * A J 6A j
0B VT (vertical tab) 2B B K 6B k
0C FF (form feed) C , C L 6C l
0D CR (carriage ret) 2D D M 6D m
0E SO (shift out) E E N 6E n
0F SI (shift in) F / F O 6F o
10 DLE (escape) P p
11 DC1 (devcontrol 1) Q q
12 DC2 (devcontrol 2) R r
13 DC3 (devcontrol 3) S s
14 DC4 (devcontrol 4) T t
15 NAK (nak) U u
16 SYN (synch idle) V v
17 ETB (end of block) W w
18 CAN (cancel) X x
19 EM (end of medium) Y y
1A SUB (substitute) A : A Z 7A z
1B ESC (escape) B ; B [ 7B {
1C FS (file separator) 3C < C \ 7C |
1D GS (group sep) D = D ] 7D }
1E RS (record sep) E > E ^ 7E ~
1F US (unit sep) F ? F _ 7F DEL

30. Conclusions "Hello World” Illustrates:
Example of simple hardware module implemented on the the RAD.
Simple test program to check if tools are running correctly.

31. “Hello, World” References
FPX Homepage
Hello World Handout
John Lockwood, David Lim, "Hello World: A simple application for the Field Programmable Port Extender (FPX), Washington University, Department of Computer Science, Technical Report WUCS-00-12, July 11, 2000.
Hello World Testbench
FPX Tool Environment