Orsay Micro-Electronics Groups Associated P. Barrillon, S. Blin, S

Orsay Micro-Electronics Groups Associated P. Barrillon, S. Blin, S
Orsay Micro-Electronics Groups Associated P. Barrillon, S. Blin, S. Callier, S. Conforti, F. Dulucq, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, N. Seguin-Moreau, V. Tocut + Wei Wei from IHEP Beijing

C. de La Taille - Administration Council
General presentation and context Technical report Administrative report Orsay, 4th July 2008 C. de La Taille - Administration Council

Microelectronics at in2p3
Large force of microelectronics experienced engineers (~40) Expertise in detectors, connectics, chip design and test Experience in designing and building large trackers Common Cadence tools Actions : Building blocks Networking poles Orsay, 4th July 2008 C. de La Taille - Administration Council

Motivation for poles Continuous increase of chip complexity (SoC, 3D…) Importance of critical mass Daily contacts and discussions between designers Sharing of well proven blocks Cross fertilization of different projects Creation of poles at in2p3 OMEGA at Orsay Strasbourg Dipole Lyon-Clermont Orsay, 4th July 2008 C. de La Taille - Administration Council

Club building blocks 0.35µm
Mission Design of basic building blocks usable by all in2p3 labs for physics experiments Motivations Target analog technology (0.35µm CMOS and SiGe AMS ) Optimize ressources and competences within in2p3 reduce developpement times Increase visibility of in2p3 in microelectronics First results 2-3 runs /yr financed by in2p3 Porquerolles workshop Fruitful exchanges Orsay, 4th July 2008 C. de La Taille - Administration Council

New club 130nm for tracking and 3D
Networking : club 130nm created at VLSI workshop Target common technology with CERN or other labs : IBM 130nm with CERN, Chartered 130nm (IBM compatible) 3D consortium : CPPM, IPHC, OMEGA, LPNHE Complementarity Task sharing Coordination IN2P3 Recommendation : participate to 3D effort in a coherent, coordinated and funded way. Orsay, 4th July 2008 C. de La Taille - Administration Council

Orsay Micro-Electronics Groups Associated
A strong team of 10 ASIC designers… = 20% of in2p3 designers = 60% of department research engineers A team with critical mass : pole created in 2007 = OMEGA Expertise in low noise, low power high level of integration ASICs 2 designers/ project 2 projects/designer Regular design meetings …Within an electronics departmt of 50 Support for tests, mesaurements, PCBs… A steady production A strong on-going R&D Building blocks SiGe 0.35µm ASPIC MAROC 2 HARDROC SKIROC SPIROC Orsay, 4th July 2008 C. de La Taille - Administration Council

Orsay micro-electronics team
8 research engineers (1 IR0, 2 IR1, 5 IR2) 1 CDD IR2 EUDET 1 phD student 1 visitor from China IHEP Beijing Orsay, 4th July 2008 C. de La Taille - Administration Council

Recent chips Several chips developped for ATLAS LAr, OPERA, LHCb, CALICE in BiCMOS 0.8µm and installed on experiments Turn to Silicon Germanium 0.35 µm SiGe BiCMOS technology in 2005 Readout for MaPMT and ILC calorimeters Very high level of integration : System on Chip (SoC) Parallel activity of building blocks ASPIC MAROC 2 HARDROC SKIROC SPIROC Orsay, 4th July 2008 C. de La Taille - Administration Council

MAROC : 64 ch MAPMT chip for ATLAS lumi
Complete front-end chip for 64 channels multi-anode photomultipliers Auto-trigger on 1/3 p.e. at 10 MHz, 12 bit charge output SiGe 0.35 µm, 12 mm2, Pd = 350mW Hold signal 64 inputs Variable Slow Shaper ns S&H Multiplexed Analog charge output S&H 64 Wilkinson 12 bit ADC Photons Multiplexed Digital charge output Variable Gain Preamp. Bipolar Fast Shaper PM 64 channels PMF Unipolar Fast Shaper 80 MHz encoder Gain correction 64*6bits 64 trigger outputs (to FPGA) 3 discris thresholds (3*12 bits) 3 DACs 12 bits LUCID Orsay, 4th July 2008 C. de La Taille - Administration Council

Active board pictures MAROC2 chip bounded at CERN 64 ch PMT MAROC side Lattice side Orsay, 4th July 2008 C. de La Taille - Administration Council

MAROC Efficiency curves
Orsay, 4th July 2008 C. de La Taille - Administration Council

ILC Challenges for electronics
Requirements for electronics Large dynamic range (15 bits) Auto-trigger on ½ MIP On chip zero suppress Front-end embedded in detector Ultra-low power : («25µW/ch) 108 channels Compactness « Tracker electronics with calorimetric performance » No chip = no detector !! Ultra-low POWER is the KEY issue ASIC Si wafers W layer ILC : 25µW/ch FLC_PHY3 18ch 10*10mm 5mW/ch ATLAS LAr FEB 128ch 400*500mm 1 W/ch Orsay, 4th July 2008 C. de La Taille - Administration Council

The front-end ASICs : the ROC chips
SPIROC Analog HCAL (SiPM) 36 ch. 32mm² June 07 Technological prototypes : full scale modules (~2m) EUDET EU funding (06-09) ECAL, AHCAL, DHCAL B=5T HARDROC Digital HCAL (RPC, µmegas or GEMs) 64 ch. 16mm² Sept 06 SKIROC ECAL (Si PIN diode) 36 ch. 20mm² Nov 06 Orsay, 4th July 2008 C. de La Taille - Administration Council

DHCAL chip : HaRDROC Hadronic Rpc Detector Read Out Chip (Sept 06) 64 inputs, preamp + shaper+ 2 discris + memory + Full power pulsing Compatible with 1st and 2nd generation DAQ : token ring readout of up to 100 chips First test of 2nd generation DAQ First test detector integration Collaboration with IPNL/LLR/Madrid/Protvino 1m3 scalable detector Production of 5000 chips in 2009 Orsay, 4th July 2008 C. de La Taille - Administration Council

HaRDROC architecture Variable gain (6bits) current preamps (50ohm input) One multiplexed analog output (12bit) Auto-trigger on ½ MIP Store all channels and BCID for every hit. Depth = 128 bits Data format : 128(depth)*[2bit*64ch+24bit(BCID)+8bit(Header)] = 20kbits Power dissipation : 1.5 mW/ch (unpulsed)-> 15µW with 1% cycle Large flexibility via >500 slow control settings Orsay, 4th July 2008 C. de La Taille - Administration Council

S-curves of 64 channels 10 bit DAC for threshold Noise ~ 1 UDAC (2mV)
Pedestal dispersion : 0.4 UDAC rms Gain dispersion 3% rms Crosstalk : < 2% 50% trigger versus channel number 30 fC 10 fC Pedestal Dac unit Channel number Orsay, 4th July 2008 C. de La Taille - Administration Council

SKIROC for W-Si ECAL Silicon Kalorimeter Integrated Read Out Chip (Nov 06) 36 channels with 15 bits Preamp + bi-gain shaper + autotrigger + analog memory + Wilkinson ADC Digital part outside in a FPGA for lack of time and increased flexibility Technology SiGe 0.35µm AMS. Chip received may 07 1 MIP in SKIROC Orsay, 4th July 2008 C. de La Taille - Administration Council

Front-end board for ECAL
No component  All features embedded in ASIC PCB – FRONT PCB – BACK An ASU (Active Sensor Unit) VFE ASIC bonded in a PCB ASIC buried in the PCB ASU stitching : zero thickness connection Orsay, 4th July 2008 C. de La Taille - Administration Council

Global dimensions : 180*180 mm, thickness 1.2mm
FEV5 : new PCB for ECAL Physical prototype Global dimensions : 180*180 mm, thickness 1.2mm pixel dimensions : 4*4 mm 0.15mm <depth<0.17mm 0.6mm< depth<0.7mm Orsay, 4th July 2008 C. de La Taille - Administration Council

12 bit Wilkinson ADC performance
rms = 0.9UADC (330µV) MIP =3 UADC 1080 1050 Noise in low gain shaper Pedestal value vs Channel number rms = 4UADC (1.4mV) MIP=30UADC 5 4 Noise vs Channel number Noise in high gain shaper Orsay, 4th July 2008 C. de La Taille - Administration Council

Second generation chip for SiPM
SPIROC : Silicon Photomul. Integrated Readout Chip 36 channels Charge measurement Time measurement Autotrigger on MIP or spe Sparsified readout compatible with EUDET 2nd generation DAQ Chips daisy-chained Pulsed power -> 25 µW/ch Fabricated in SiGe AMS 0.35 µm Submitted in june 07 Chip area : 30 mm2 Orsay, 4th July 2008 C. de La Taille - Administration Council

SPIROC main features Internal input 8-bit DAC (0-5V) for individual SiPM gain adjustment Energy measurement : 14 bits 2 gains (1-10) + 12 bit ADC 1 pe  2000 pe Variable shaping time from 50ns to 100ns pe/noise ratio : 11 Auto-trigger on 1/3 pe (50fC) pe/noise ratio on trigger channel : 24 Fast shaper : ~10ns Auto-Trigger on ½ pe Time measurement : 12-bit Bunch Crossing ID 12 bit TDC step~100 ps Analog memory for time and charge measurement : depth = 16 Low consumption : ~25µW per channel (in power pulsing mode) Individually addressable calibration injection capacitance Embedded bandgap for voltage references Embedded 10 bit DAC for trigger threshold and gain selection Multiplexed analog output for physics prototype DAQ 4k internal memory and Daisy chain readout Orsay, 4th July 2008 C. de La Taille - Administration Council

SPIROC : One channel schematic
ns 50-100ns Gain selection 4-bit threshold adjustment 10-bit DAC 15ns DAC output HOLD Slow Shaper Fast Shaper Time measurement Charge measurement TDC ramp 300ns/5 µs 12-bit Wilkinson ADC Trigger Depth 16 Common to the 36 channels 8-bit DAC 0-5V Low gain Preamplifier High gain Preamplifier Analog memory 15pF 1.5pF 0.1pF-1.5pF Conversion 80 µs READ Variable delay IN Discri Gain Flag TDC IN test Orsay, 4th July 2008 C. de La Taille - Administration Council

Acquisition Channel 0 Conversion ADC + readout Ecriture RAM Channel 1
ValidHoldAnalogb 16 RazRangN Chipsat 16 ReadMesureb 16 Acquisition NoTrig gain Trigger discri Output Wilkinson ADC Discri output ExtSigmaTM (OR36) StartAcqt SlowClock Hit channel register 16 x 36 x 1 bits TM (Discri trigger) 36 BCID 16 x 8 bits Channel 0 gain Trigger discri Output Wilkinson ADC Discri output Conversion ADC + Ecriture RAM StartConvDAQb 36 ValGain (low gain or high Gain) TransmitOn readout RamFull OutSerie 36 EndReadOut EndRamp (Discri ADC Wilkinson) StartReadOut FlagTDC Rstb Channel 1 Clk40MHz ..… ADC ramp Startrampb (wilkinson ramp) RAM OR36 … StartRampTDC TDC ramp ChipID Chip ID register 8 bits 8 ValDimGray DAQ ASIC ValDimGray 12 bits 12 Orsay, 4th July 2008 C. de La Taille - Administration Council

SPIROC performance Good analog performance Single photo-electron/noise = 8 Auto-trigger with good uniformity Complex chip : many more measurements needed bug in the ADC necessitates an iteration Orsay, 4th July 2008 C. de La Taille - Administration Council

ASPIC Multichannel CCD readout for LSST Collab LAL-LPNHE Test of Clamp&Sample or Dual Slope Integrator Low noise (<5 e-) Ultra low crosstalk (<0.01%) Aim for a 16 channel chip Orsay, 4th July 2008 C. de La Taille - Administration Council

PMm2 : large photodection area
“PMm2” (2006 – 2009), funded by the ANR : LAL, IPNO, LAPP and Photonis Replace large PMTs (20”) by groups of smaller ones (12”) central 16ch ASIC (PaRISROC) 12 bit charge + 12 bit time water-tight, common High Voltage Only one wire out (DATA + VCC) Target low cost Reuse many parts from MAROC & SPIROC Application : large water Cerenkov neutrino 1ns time resolution High granularity scalability Joël Pouthas IPN Orsay Orsay, 4th July 2008 C. de La Taille - Administration Council

PArISROC specifications
Based on a complete 16 channels read out chip with dedicated for Photomultiplier array (PARISROC) Measurement of Charge and time A complete front end chip with 64 channels was submitted in last June and expected in this October. I would like remind you of MAROC1 functionality blocks. MAROC1 contains/is composed of a variable gain preamplifier to adjust the PM gain per channel from 0 to 4. We have one multiplexed charge output where we can change the peaking time of slow shaper from 20ns to 200ns. Otherwise there are 64 trigger outputs which can be due to Bipolar Fast shaper or Unipolar Fast Shaper The unipolar Fast Shaper is followed by 3 discriminators to close to LUCID needs Each threshold is fixed by internal DAC Orsay, 4th July 2008 C. de La Taille - Administration Council

ASIC Architecture Channel 16 Internal read Channel 1 Vref SSH CRRC2 Slow Shaper (50 , 100, 200 ns) Track & hold 12 bits ADC 1 digital charge output Variable Gain Amplifier (1-8) 16 charge inputs 1 ext. Common Hold OR Differential Fast Shaper (15ns) variable delay 1 OR output OR Gain Correction (8bits) Discri 16 Trigger outputs Mettre en couleur les nouveaux bloc: pa et CRRC2 Faire un transparent ou ajouter un bloc pour la partie numerique DAC 4 bits Vref SSH Vref FSH Threshold (4bits/ch) 24 bits counter 10MHz new blocks slow control signal Bandgap DAC 10 bits 24bits absolute time measurement Threshold Orsay, 4th July 2008 C. de La Taille - Administration Council

3D technology Increasing integration density, mixing technologies Wafer thinning to <50 µm Minimization of interconnects Large industrial demand Processors, image sensors… ©A. Klumpp (IZM) No side connections Without intervention in IC fabrication Wafer to wafer, Chip to Wafer Orsay, 4th July 2008 C. de La Taille - Administration Council

Conclusion MAROC, HaRDROC, SKIROC, SPIROC… 4 complex ASICs prototyped in 2007 : 2nd generation chips SoC : System on chip (ADC, TDC, DAQ…) Production in 2008 in a dedicated run ILC main customer Many external requests Long and difficult measurements… Coming up : 3D CMOS 130nm Basic analog tier for 3D integration in collaboration with CPPM Marseille aimed at 50x50µm pixels simple readout. Orsay, 4th July 2008 C. de La Taille - Administration Council

Collaborations LSST ( ) with LPNHE ILC Si-W ECAL ( ) with LLR & LPCClermont ILC RPC-Fe DHCAL (2006-) with LLR, IPNL & LAPP ILC Scintillator (SiPM)-Fe AHCAL (2003-) with DESY ILC Scintillator (SiPM)-W ECAL(2005-) with KEK ATLAS luminometer ALFA ( ) with CERN ATLAS luminometer LUCID ( ) with Bologna ATLAS tracker (2007-) with CPPM, Bonn, Munich & LBL Double Chooz ( ) with NEVIS lab PMm² ( ) with IPNO & LAPP SuperNemo Front-end (2008-) with Bordeaux SuperNemo SNATS (2008-) with LPCCaen SymbolX (2008-) with APC North Auger ( ) with IPNO Medical imaging with MaPMT (2007-) with ISS Roma Medical imaging PET with MsiPM (2007-) with INFN Pisa Medical imaging with MaPMT ( ) with IMNC Medical imaging with MaPMT (2008-) with CSNSM Balloon experiment with SiPM (2008-) with Aachen Generic detector R&D (2007-) Space telescope for EECR measurement (2006-) with EHWA Korea FJPPL (2006-) with KEK FCPPL (2007-) with IHEP Beijing Orsay, 4th July 2008 C. de La Taille - Administration Council

Collaboration  Commitments
ATLAS luminometry: roman pots readout MAROC2 for MultiAnode PMT [S. Blin] CALICE/EUDET ILC calorimeters readout ASICs HaRDROC for RPC DHCAL (ANR 2007) [N. Seguin] SKIROC for SiW ECAL (EUDET ) [J. Fleury] SPIROC for SiPM AHCAL (and japanese ECAL) (EUDET) [L. Raux] Full production beg 2009 Coordination of FP6 EUDET JRA3 (with S. Sefkow DESY) LSST : focal plane CCDs readout chip ASPIC (collab LPNHE) [V. Tocut] PMM2 : ANR large area photodectors PARISROC [G. Martin] ATLAS 3D tracker R&D Orsay, 4th July 2008 C. de La Taille - Administration Council

Collaboration  External contracts
European contract EUDET ( ) R&D for detectors at the ILC. Calorimetry : design of chips for ECAL, AHCAL and DHCAL. 36 ppm engineer + 130k€ chip foundries ANR PMm2 ( ) R&D for large arrays of photomyultipliers (“square meter PM”). ANR DHCAL ( ) R&D for a cubic meter digital hadron calorimeter at the ILC. 140k€ chip foundry for 5000 chips ANR vitesse ( ) 3D electronics for trackers. R&D for ATLAS at SLHC. Orsay, 4th July 2008 C. de La Taille - Administration Council

Collaboration  Requests
MAROC2/3 ATLAS LUCID detector (Bologna) Double Chooz (Nevis USA) PET imaging with PMT64 (ISS Roma) Medical imaging with SiPM matrixes (INFN Pisa) Air shower imaging (EHWA Seoul) HaRDROC Medical imaging Trecam (IMNC Orsay) Xray satellite (CSNSM Orsay) Xray SiPM Balloon experiment (Aachen) SPIROC SiPM readout (KEK Japan) ASPIC CCD readout (Japan/New Zealand) PARISROC SNEMO MEdical imaging (INFN Pisa) Orsay, 4th July 2008 C. de La Taille - Administration Council

Collaboration  International Joint Labs
Japan : FJPPL (2006-) Collaboration with KEK group (M Tanaka) on ASIC R&D for megaton-like experiment linked to PMm². One Maroc test board supplied. China : FCPPL (2007-) Collaboration with IHEP (Beijing). One Chinese visitor for 6 months (1/2/08 31/7/08) on photomultiplier readout design. Collaboration on Parisroc and Building blocks. One Chinese PhD student (1/9/081/9/09). Orsay, 4th July 2008 C. de La Taille - Administration Council

Manpower  Position in Omega - 2008
% ANR EU IN2P3 TOTAL PMm² DHCAL VITESSE 2008 EUDET 2006 LSST SuperNemo ATLAS Lumi ANR+EU GRAND Pierre Barrillon 30 70 100 Sylvie Blin 50 Stéphane Callier Selma Conforti Frederic Dulucq Julien Fleury Christophe de La Taille 15 25 10 Gisèle Martin 20 Ludovic Raux Nathalie Seguin Vanessa Tocut 60 90 Wei Wei TOTAL FTE 2.25 1.25 0.8 4.2 0.7 1.45 8.6 2.8 11.4 Orsay, 4th July 2008 C. de La Taille - Administration Council

Financial summary Omega operating budget That line is twofold. It funds Omega for its general operating needs (internal testboard, additional packaging, bonding, internal store covering, etc.) and it covers the equipment requirements (Die storage, computers, furniture, etc.) 2008 operating credits needed: € 2008 operating credits granted: 0 € 2008 equipment credits needed: € 2008 equipment credits granted: 0€ External services budget That line is used to embank invoices from products sold by Omega. It is also used to pay for the test boards and ASICs sold. It allows providing test boards for labs to test our ASICs and eventually start a collaboration if the ASICs correctly fit the experiment requirements. 2008 credits needed: € 2008 credits granted: 0 € 2008 external resources 30 000€ 2008 spent (1/7/08) 25 000€ Travel assignment The mission assignment line is used to expense travels operated for pole aim, such as pole presentation or technical mission assignment for research promoting trade essentially for medical imaging. 2008 credits needed: € 2008 credits granted: 0€ 2008 spent (1/7/08) 5 000€ Orsay, 4th July 2008 C. de La Taille - Administration Council

Communication  talks in conferences
Photo Detector ’07, Kobe June, 29th, 2007 Invited Talk - Integrated electronics for SiPM, J. Fleury TWEPP ’07, Prague Sept, 5th, 2007 Talk – Hardroc presentation, N. Seguin Moreau Talk – MAROC presentation, P. Barrillon Poster – Digital part of Spiroc, F. Dulucq Poster – Analogue part of Spiroc, L.Raux Poster – Skiroc presentation, J. Fleury IEEE – Nuclear Science Symposium, Honolulu Oct, 31st, 2007 Talk - A front-end chip to read out the imaging Si-W calo for ILC, J. Fleury Talk - Hardroc, N. Seguin-Moreau Talk - Spiroc, C. de la Taille Poster – ROC chip, digital, F. Dulucq Poster – MAROC chip, P. Barrillon ASPERA R&D astroparticle physics meeting, Lisbon Jan, 8th, 2008 Talk – Integrated front-end electronics for astroparticle, J. Fleury CALOR ’08, Pisa May, 28th, 2008 Talk – 2nd generation ASICs for CALICE/EUDET calorimeters, C. de La Taille NDIP ’08, Aix-les-bains June, 4th, 2008 Tutorial – Tutorial on readout electronics for photodetectors, C. de La Taille Talk - SPIROC : Silicon PM readout chip Orsay, 4th July 2008 C. de La Taille - Administration Council

Communication  Web site [P. Barrillon]
Provide up-to-date datasheets, application notes, firmware, etc. Orsay, 4th July 2008 C. de La Taille - Administration Council

Teaching • Gisèle Martin Chassard Supelec, analogue microelectronics, labs, 20h • Nathalie Seguin-Moreau Master MIP, analogue electronics, lectures and training, ups, 9h • Vanessa Tocut ISEP, analogue and mixed electronics, lectures and training, 60h • Julien Fleury ENSTA, digital electronics, training, 24h • Ludovic Raux • Sylvie Blin ISEP, mixed electronics, training, 60h • Christophe de La Taille Supelec, analogue electronics, lectures, training and labs, 40h • Stephane Callier ESIEE, RF&HF measurement, labs, 16h EFREI, mixed microelectronics, lectures and training, 30h Orsay, 4th July 2008 C. de La Taille - Administration Council

Summary Positive An IR2 position in 2008 from IN2P3 A good international visibility A good collaboration with CSNSM, IPNO & LLR Negative No budget (yet) from in2p3 (but there should be one on an identified line for 2009) Weak coupling with test group position inside the lab and the electronics dept Orsay, 4th July 2008 C. de La Taille - Administration Council

Questions & Comments Orsay, 4th July 2008 C. de La Taille - Administration Council

Annexes Cost of ASICS Testboards Collaboration details Orsay, 4th July 2008 C. de La Taille - Administration Council

Multi Project Run vs Dedicated Run
HARDROC2: will be submitted in june 08 (MPW run) MPW: 1k€/mm2 => Hardroc= 25 k€ 25 dies delivered in September 08, to be packaged About 300 dies available (no guaranty): 100 euros/die + packaging Price : 25 k€ € * nb_chips Engineering run: Wafer 8’’ Available area= mm2 1 reticle=20x20 mm2=400 mm2 => 65 reticles/wafer 16 chips (25 mm2) / reticle => 1000 Hardroc/wafer Cost : 150 k€ (masks) + 5k€/wafer - Price : 150 k€ + 5 € * nb_chips valuable for more than 1250 chips Orsay, 4th July 2008 C. de La Taille - Administration Council

TEST BOARD MAROC (COB) 64ch PM socket USB port GPIB port Control Altera You can see the test board with chip on board The oscillation problem have been almost solved by chip on board There are no longer oscillations at gain lower than 2 Orsay, 4th July 2008 C. de La Taille - Administration Council

Collaboration : details (1/3)
LSST ( ) Omega is part of the LSST collaboration. It is designing the CCD camera front-end ASIC ‘ASPIC’ in collaboration with LPNHE Paris. ILC Si-W ECAL ( ) The Si-W ECAL prototypes designed within the CALICE/EUDET collaboration is read out with Omega ASICs (‘FLC_PHY3’ and ‘SKIROC’ in collaboration with LPC Clermont).Prototypes funded by EUDET FP6 program. Production of 1000 ASICs in 2009 ILC RPC-Fe DHCAL (2006-) Omega is designing a read-out ASIC for the RPC digital HCAL (‘HARDROC’) within the CALICE collaboration. Production of 5000 chips in 2009. ILC Scintillator (SiPM)-Fe AHCAL (2003-) Omega is designing a read-out ASIC for the Scintillator SiPM Analogue HCAL (‘SPIROC’) within the CALICE/EUDET collaboration. Production of 1000 chips in 2009. ILC Scintillator (SiPM)-W ECAL(2005-) Front-end electronics designed for ILC AHCAL is reused to read-out the Sci-Fe ECAL designed by the KEK group within the CALICE collaboration. Omega is providing technical support on that detector electronics. ATLAS luminometer ALFA ( ) Omega is part of the ALFA luminometer collaboration and has designed the MA-PM read-out ASIC (‘MAROC2’). ATLAS luminometer LUCID ( ) Omega is part of the LUCID luminometer collaboration and has designed the MA-PM read-out ASIC (‘MAROC3’) ASICs produced in 2008. ATLAS tracker (2007-) Omega is part of the collaboration on 3D electronics R&D for ATLAS tracker. Orsay, 4th July 2008 C. de La Taille - Administration Council

Double Chooz ( ) Omega has provided a small production of MAROC2 chips to readout the muon veto tagger ASICs produced in 2008 PMm² ( ) Omega is part of the generic research program PMm² (funded by ANR) aimed to reduce cost on high area of PM detectors. An ASIC (‘PARISROC’) has been designed for that program SuperNemo Front-end (2008-) A readout ASIC (PARISROC) has been designed to read out the supernemo calorimeter. SuperNemo SNATS (2008-) Omega has designed a time stamper in collaboration with LPC Caen for supernemo calorimeter. SymbolX (2008-) A Maroc test board has been provided by Omega to perform irradiation tests for the spatial experiment. SymbolX by APC lab. North Auger ( ) Omega has designed a set of current-feedback operational amplifiers prototypes to read out PM for the north auger collaboration Medical imaging ISS Roma (2007-) Omega provides chips and test boards to Roma lab for medical imaging applications (PET cameras) Medical imaging INFN Pisa (2007-) Omega provides chips and testboards to INFN Pisa lab for medical imaging applications (PET cameras). Medical imaging IMNC ( ) Omega provides HARDROC chips and support for PCB design of the TRECAM camera to IMNC for medical imaging applications. Orsay, 4th July 2008 C. de La Taille - Administration Council

Balloon experiment Aachen (2008-) Omega provides HARDROC chips and testboards to Aachen lab for balloon experiment applications. Generic detector R&D (2007-) Omega provides electronics for SiPM R&D to readout SiPM matrices (LAL Detector group) Space telescope for EECR measurement (2006-) Omega provides MAROC chips to Korean EWHA physics group to read out MAPMT for a space telescope aimed to EECR measurement. FJPPL (2006-) Collaboration with KEK group (M Tanaka) on ASIC R&D for megaton-like experiment linked to PMm². One Maroc test board supplied. FCPPL (2007-) Collaboration with IHEP (Beijing). One Chinese visitor for 6 months (1/2/08 31/7/08) on photomultiplier readout design. Collaboration on Parisroc and Building blocks. One Chinese PhD student (1/9/081/9/09). Orsay, 4th July 2008 C. de La Taille - Administration Council

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