1. DHH progress report Igor Konorov TUM, Physics Department, E18
7-th International Work Shop on DEPFET detectors and applications
Ringberg –May 8-11, 2011
Outline:
DHH architecture
DHH prototype
Summary and outlook

2. 7-th Int WS on DEPFET detectors and applications И.Коноров, TUM
DHH interfaces
FTSW
DHH
Controller
Timing
JTAG
Copper
Timing
JTAG
Optical
PXD DAQ
DHP
GCK, FCK
TRG, RST
DHH
JTAG
DATA(3:0)
DATA(3:0)
Optical
Copper
7-th Int WS on DEPFET detectors and applications И.Коноров, TUM

3. DHH prototype development
Objectives
Full readout chain test
4xDHP
ATCA DAQ
Belle Trigger Distribution system
Slow control, JTAG
Lab setup support
Ethernet
JTAG
Firmware development
Finalize DHH functionality
7-th Int WS on DEPFET detectors and applications И.Коноров, TUM

4. 7-th Int WS on DEPFET detectors and applications И.Коноров, TUM
DHP – DHH interface
To DHP
GCK (LVDS/2.5V) – 3/20 of MHz = MHz
FCK (LVDS/2.5V) – Frame clock about 50 kHz
TRG (LVDS/2.5V)
RST (LVDS/2.5V)
From DHP
DATA (0 : 1.6 Gb/s
7-th Int WS on DEPFET detectors and applications И.Коноров, TUM

5. 7-th Int WS on DEPFET detectors and applications И.Коноров, TUM
DHH prototype module
I/O isolation DC/DC converter up to 1500 V
FPGA: Virtex6VLX75T
128 MB DDR2 memory for soft core CPU
SODIMM socket
Clustering ASIC
7-th Int WS on DEPFET detectors and applications И.Коноров, TUM

6. 7-th Int WS on DEPFET detectors and applications И.Коноров, TUM
DHH prototype module
3x RJ45
Ethernet
Timing (Belle)
JTAG (Belle)
2xSFP+ for DAQ interfaces
2x6Gb/s SFP+
SFP for DHH controller interface
2xInfiniband 4x connectors for DHP
7-th Int WS on DEPFET detectors and applications И.Коноров, TUM

7. 7-th Int WS on DEPFET detectors and applications И.Коноров, TUM
Infiniband cables
Infiniband cable 4x:
Gb/s
8 differential pairs
1% crosstalk
radiation hardness ?
7-th Int WS on DEPFET detectors and applications И.Коноров, TUM

8. 7-th Int WS on DEPFET detectors and applications И.Коноров, TUM
DHP interface
Infiniband connector I
GCK, FCK, TRG, RST
DATA(3:0)
Infiniband connector II
JTAG LVDS
4 pairs free for future
7-th Int WS on DEPFET detectors and applications И.Коноров, TUM

9. 7-th Int WS on DEPFET detectors and applications И.Коноров, TUM
New requirements
SODIMM connector for clustering ASIC
Remote control of DHP JTAG IO power
Switch of power of JTAG signals when DHP is not powered
Support of DCD monitor signal ?
Extra connectors for existing DHP test setup
SMT high speed serial links
General purpose LVDS signals
7-th Int WS on DEPFET detectors and applications И.Коноров, TUM

10. 7-th Int WS on DEPFET detectors and applications И.Коноров, TUM
DHH status
Schematic in progress
Complete
Power, Serial links, Flash interfaces, clock jitter cleaner
New requirements to be implemented
Plans
Finalize schematic in collaboration with Bonn in order to start production in end of June
Remark
Project is delayed by 4 month but no impact on overall schedule
7-th Int WS on DEPFET detectors and applications И.Коноров, TUM