2. Introduction Introduction to VHDL Entities Signals Data & Scalar Types
Arrays & Records
Logical & Numerical Operators

3. Hardware Description Languages (HDL)

4. Description Levels

5. What a designer really needs ?!

6. Why VHDL ?!

7. Before VHDL ..

8. Now with VHDL ..

9. Entities

10. Elements of an Entity

11. Elements of an Entity

12. Architectures

13. Behavioral Description

14. Behavioral Description

15. Behavioral Description

16. Behavioral Description

17. Packages .. !!

18. Packages in VHDL

19. Predefined Packages

20. Signals

21. Signals: bit & vectors

22. Vector’s width & order

23. Vector’s width & order

24. External vs. Internal Signals

25. Declaration of signals

26. Documentation

27. Documentation

28. Generic .. ?!

29. Generic Specification

30. Generic Applications

31. Generic Applications

32. Scalar type

33. Scalar type

34. Scalar type

35. Scalar type

36. Scalar type

37. Arrays

38. User-defined-arrays

39. Records

40. Logical Operators

41. Numerical Operators

42. Numerical Operators

43. Numerical Operators

44. Numerical Operators

45. Numerical Operators

46. Numerical Operators

47. Numerical Operators

48. Numerical Operators

49. Relational Operators

50. Constants

51. Use of Constants

52. Generic vs. Constant

53. Generic vs. Constant

54. Generic vs. Constant

55. Summary Introduction to VHDL Entities Signals Data & Scalar Types
Arrays & Records
Logical & Numerical Operators

57. Content Process Signals vs. Variables Conditional statement Loops
Sequential & Parallel design
Signals & Modules
Test Bench
Reporting

58. Structure of process

59. Structure of process

60. Structure of process

61. Structure of process

62. Structure of process

63. Process Execution

64. Sensitivity list and Signals in a Process

65. Sensitivity list and Variables in a Process

66. Sensitivity list and Variables in a Process

67. Sensitivity list and Variables in a Process

68. Signals vs. Variables

69. Signals vs. Variables

70. Signals vs. Variables

71. Controlling the sequence of statements

72. Conditional statements

73. Conditional statements

74. Conditional statements

75. Conditional statements with alternatives

76. Conditional statements with alternatives

77. Multiple Choices

78. Multiple Choices

79. Loop with a counter

80. Loop with a counter

81. Loop with a counter

82. Loop with a counter

83. The world is not sequential .. !!

84. How an architecture is executed

85. How an architecture is executed

86. How an architecture is executed

87. How an architecture is executed

88. Do you really need a process ?!

89. Do you really need a process ?!

90. Conditional Signal assignments

91. Conditional Signal assignments

92. Selected Signal assignment

93. Selected Signal assignment

94. Signals and modules

95. Signals and modules

96. Multi-level logic

97. Multi-level logic

98. Multi-level logic

99. Multi-level logic

100. Structural design

101. Elements of structural descriptions

102. Positional port mapping

103. Named port association

104. Complex port mapping

105. Component declaration

106. Component instantiation

107. Test Bench .. ?!

108. VHDL test bench

109. Elements of a VHDL test bench

110. Elements of a VHDL test bench

111. Using test benches

112. Using test benches

113. Using test benches

114. Using test benches

115. Unit Under Test

116. Unit Under Test

117. Unit Under Test

118. Unit Under Test

119. Stimuli of signals

120. Assert statement

121. Reporting with assertions

122. Summary Process Signals vs. Variables Conditional statement Loops
Sequential & Parallel design
Signals & Modules
Test Bench
Reporting

123. Good luck 

125. Finite State Machines (FSM)
All programmable logic designs can be specified in Boolean form.
However some designs are easier to conceptualize and implement using non-Boolean models.
The State Machine model is one such model.

126. FSM
A state machine represents a system as a set of states, the transitions between them, along with the associated inputs and outputs.
So, a state machine is a particular conceptualization of a particular sequential circuit.
State machines can be used for many other things beyond logic design and computer architecture.

127. FSM Any Circuit with Memory Is a Finite State Machine
Even computers can be viewed as huge FSMs
Design of FSMs Involves
Defining states
Defining transitions between states
Optimization / minimization

128. Definition of Terms State Diagram
Illustrates the form and function of a state machine. Usually drawn as a bubble-and-arrow diagram.
State
A uniquely identifiable set of values measured at various points in a digital system.

129. Definition of Terms Next State
The state to which the state machine makes the next transition, determined by the inputs present when the device is clocked.
Branch
A change from present state to next state.

130. Definition of Terms Mealy Machine
A state machine that determines its outputs from the present state and from the inputs.
Moore Machine
A state machine that determines its outputs from the present state only.

131. Present and Next State State 0 State 1 State 3 State 2
For any given state, there is a finite number of possible next states.
On each clock cycle, the state machine branches to the next state.
One of the possible next states becomes the new present state, depending on the inputs present on the clock cycle.
State 2
State 3
State 1
State 0

132. Describe Outputs as Concurrent Statements Depending on State Only
Moore Machine
Describe Outputs as Concurrent Statements Depending on State Only
transition
condition 1
state 2 /
output 2
state 1 /
output 1
transition
condition 2

133. transition condition 1 / transition condition 2 /
Mealy Machine
Describe Outputs as Concurrent Statements Depending on State and Inputs
transition condition 1 /
output 1
state 2
state 1
transition condition 2 /
output 2

134. Moore and Mealy FSMs Can Be Functionally Equivalent
Moore vs. Mealy FSM (1)
Moore and Mealy FSMs Can Be Functionally Equivalent
Mealy FSM Has Richer Description and Usually Requires Smaller Number of States
Smaller circuit area

135. Mealy FSM Computes Outputs as soon as Inputs Change
Moore vs. Mealy FSM (2)
Mealy FSM Computes Outputs as soon as Inputs Change
Mealy FSM responds one clock cycle sooner than equivalent Moore FSM
Moore FSM Has No Combinational Path Between Inputs and Outputs
Moore FSM is less likely to have a shorter critical path

136. Moore FSM Input: w Transition function Next State: y_next
Present State:
y_present
Memory
(register)
Output
function
Output: z

137. Mealy FSM Input: w Transition function Next State Present State: y
Memory
(register)
Transition
function
Output
Input: w
Present State: y
Next State
Output: z

138. Moore FSM that Recognizes Sequence 10
Moore FSM - Example
Moore FSM that Recognizes Sequence 10
S0 / 0
S1 / 0
S2 / 1 1
reset
S0: No
elements
of the
sequence
observed
S1: “1”
observed
S1: “10”
observed
Meaning
of states:

139. Mealy FSM that Recognizes Sequence 10
Mealy FSM - Example
Mealy FSM that Recognizes Sequence 10
0 / 0
1 / 0
1 / 0 S0 S1
reset
0 / 1
S0: No
elements
of the
sequence
observed
S1: “1”
observed
Meaning
of states:

140. Moore & Mealy FSMs – Examples
clock
input
S S S S S0
Moore
S S S S S0
Mealy

141. FSMs in VHDL
Finite State Machines Can Be Easily Described With Processes
Synthesis Tools Understand FSM Description If Certain Rules Are Followed
State transitions should be described in a process sensitive to clock and asynchronous reset signals only
Outputs described as concurrent statements outside the process

142. State Encoding Problem
State Encoding Can Have a Big Influence on Optimality of the FSM Implementation
No methods other than checking all possible encodings are known to produce optimal circuit
Feasible for small circuits only
Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool

143. Types of State Encodings
Binary (Sequential) – States Encoded as Consecutive Binary Numbers
Small number of used flip-flops
Potentially complex transition functions leading to slow implementations
One-Hot – Only One Bit Is Active
Number of used flip-flops as big as number of states
Simple and fast transition functions
Preferable coding technique in FPGAs

144. Types of State Encodings
Binary Code
One-Hot Code S0
000 S1
001 S2
010 S3
011 S4
100 S5
101 S6
110 S7
111

145. RTL Design Components Data Inputs Control Inputs Datapath Circuit
Data Outputs

146. Datapath Circuit
Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task
Examples of Resources
Adders, Multipliers, Registers, Memories, etc.

147. Control Circuit
Controls Data Movements in Operational Circuit by Switching Multiplexers and Enabling or Disabling Resources
Follows Some ‘Program’ or Schedule
Usually Implemented as FSM

148. Example
Consider the following algorithm that gives the maximum of two numbers.
0: int x, y, z;
1: while (1) {
2: while (!start);
3: x = A;
4: y = B;
5: if (x >= y)
6: z = x;
else
7: z = y; }

149. Example – Cont.
Now, consider the following VHDL code that gives the maximum of two numbers.
entity MAX is
generic(size: integer:=4);
port( clk, reset, start: in std_logic;
x_i, y_i :in std_logic_vector(size-1 downto 0);
z_o: out std_logic_vector(size-1 downto 0));
end MAX;
architecture behavioral of MAX is
type STATE_TYPE is (S0, S1, S2, S3, S4);
signal Current_State, Next_State: STATE_TYPE;
signal x, y, mux : std_logic_vector (size-1 downto 0):= (others => '0');
signal z_sel, x_ld, y_ld, z_ld : std_logic := '0';
begin

150. Example – Cont. -----------------------------------------------
Reg_x: process (CLK)
begin
if (CLK'event and CLK='1') then
if reset='1' then
x <= (others => '0');
else
if (x_ld='1') then
x <= x_i;
end if;
end process;
Reg_y: process (CLK)
y <= (others => '0');
if (y_ld='1') then
y <= y_i;
Reg_z_o:process (CLK)
begin
if (CLK'event and CLK='1') then
if reset='1' then
z_o <= (others => '0');
else
if (z_ld='1') then
z_o <= mux;
end if;
end process;
Multiplexer: process (x, y, z_sel)
if (z_sel='0') then
mux <= x;
elsif (z_sel='1') then
mux <= y;

151. Example – Cont. -----------------------------------------------
SYNC_PROC: process (CLK, RESET)
begin
if (RESET='1') then
Current_State <= S0;
elsif (CLK'event and CLK = '1') then
Current_State <= Next_State;
end if;
end process;
COMB_PROC: process (Current_State, start, x, y, z_sel)
begin
case Current_State is
when S0 => -- idle
if (start='1') then
Next_State <= S1;
else
Next_State <= S0;
end if;
when S1 => -- x = x_i & y = y_i
x_ld <= '1'; y_ld <= '1'; z_ld <= '0'
Next_State <= S2;
when S2 => -- x ≥ y
x_ld <= '0'; y_ld <= '0';
if (x >= y ) then
Next_State <= S3;
Next_State <= S4;
when S3 => -- z = x
z_sel <= '0';
z_ld<=’1’;
when S4 => -- z = y
z_sel <= '1';
end case;
end process;

152. Now, What’s Next ?!