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Day 15: October 10, 2012 Inverter Performance
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 15: October 10, 2012 Inverter Performance Penn ESE370 Fall DeHon
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Previously Delay as RC-charging Transistor Capacitance Drive Current
As a function of geometry (W/L) Penn ESE370 Fall DeHon
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Today Sizing Large Fanout Capacitance Revisited Miller Effect
Parallel Gate Capacitance Penn ESE370 Fall DeHon
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Transistor Sizing What happens to Ids as a function of W?
What happens to Cg as a function of W? Conclude: faster transistors present more load on their inputs Penn ESE370 Fall DeHon
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First Order Delay R0 = Resistance of minimum size NMOS device
C0 = gate capacitance of minimum size NMOS device Rdrive = R0/W Cg = WC0 Penn ESE370 Fall DeHon
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t model All delays are RC delays Always have an R0C0 term t = R0C0
Express all delays in t units Like l units for measurement Separate delay into Technology dependent term t = R0C0 Technology independent term Penn ESE370 Fall DeHon
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Inverter Sizing What is the impact of the delay on the middle inverter if double size of all the transistors? Penn ESE370 Fall DeHon
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How Size How size to equalize Rise and Fall?
mn=500cm2/Vs, mp=200cm2/Vs When velocity saturated Rdrive=R0/2 Penn ESE370 Fall DeHon
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SPICE Simulation Penn ESE370 Fall DeHon
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Worst Case Delay Largest R Rdrive = max(Rpullup,Rpulldown)
If equalize Rpullup and Rpulldown Rdrive = Rpullup=Rpulldown Penn ESE370 Fall DeHon
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Equalizing Delay For simplicity, for today Assume Wp=Wn equalizes Ids
Penn ESE370 Fall DeHon
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Large Fanout What is delay if must drive fanout=100?
Penn ESE370 Fall DeHon
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What Delay? What is delay here? Penn ESE370 Fall DeHon
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How Size How size transistors to minimize delay?
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Optimizing Delay = 2Wmid/1 + 200/Wmid How minimize?
D(Delay)/D(Wmid) = 0 2 – 200/(Wmid)2=0 Wmid=sqrt(100) = 10 Penn ESE370 Fall DeHon
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Delay? Delay at optimal Wmid? Penn ESE370 Fall DeHon
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Try again What is the delay here? Penn ESE370 Fall DeHon
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…and Again Delay here? Penn ESE370 Fall DeHon
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Lesson Don’t drive large fanout with a single stage
Must scale up over a number of stages …but not too many Exact number will be technology dependent Penn ESE370 Fall DeHon
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Charge on Capacitors Penn ESE370 Fall DeHon
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Questions What is DQ when switched? Equivalent Capacitance?
Contribution from each transistor? Penn ESE370 Fall DeHon
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Gate-Drain Capacitance
What is the voltage across Vin—V2 When Vin=Vdd When Vin=Gnd What is DV across Vin—V2 when Vin switches from Vdd to Gnd? Penn ESE370 Fall DeHon
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Miller Effect For an inverting gate
Capacitance between input and output must swing 2 Vhigh Or…acts as double-sized capacitor Penn ESE370 Fall DeHon
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Admin Drop Date Friday HW5 out More work than HW4 Get started early
Ramping up for Project Penn ESE370 Fall DeHon
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Ideas First order delay reason in t=R0C0 units
Scaling everything up doesn’t help Drive large capacitive loads in stages Penn ESE370 Fall DeHon
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