1. LNN Reversible Circuit Realization Using Fast Harmony Search Based Heuristic
Mohammad Gh. Alfailakawi,
Imtiaz Ahmad, Suha Hamdan
Computer Engineering Department
College of Computing Sciences & Engineering
Kuwait University

2. Overview Motivation Goal Reversible circuits & Quantum Cost
Problem formulation
Experimental results
Conclusion & future work
APCSEE'14
11/9/14

3. Why Reversible Circuits?
Current technology reaching physical limits
Quantum computation is the leading technology to replace current one
Features of quantum computing:
Exponential speedup
Low power
Reversibility
Thus, studies on reversible circuits are booming
APCSEE'14
11/9/14

4. Goal Optimize realization of reversible circuit in LNN architecture by
Reordering input line to reduce cost
Extend earlier work that uses “swap pairs”
How to find best “swap” to avoid swap back
By extending algorithm (Harmony Search) with a local optimization
APCSEE'14
11/9/14

5. What is a Reversible Circuit?
Cascade of reversible elements (gates)
Quantum gates used due to inherit reversibility
Number of inputs = number of outputs
No feedback and no fan-out
APCSEE'14
11/9/14

6. Quantum Gates NOT : traditional NOT CNOT/sqrt/inv-sqrt:
Operate on two lines (qubits): control and target
Performs NOT/sqrt/inv-sqrt function if control line is set
Known as NCV library
Control
Target
APCSEE'14
11/9/14

7. Cost Metric: Quantum Cost
Number of elementary gates used in circuit
If circuit designed using complex gates (MCT)
Need to be composed to one with only elementary gates
APCSEE'14
11/9/14

8. LNN Architecture
Certain Quantum technologies require 2-qubit gate lines to be physically adjacent
i.e. Trapped ions, liquid state NMR
Distant target/control lines must be brought together
Using SWAP gates (or chain of such gates)
SWAP gates increased quantum cost of circuit
Each SWAP has quantum cost of 3
A common optimization in such technology is to reduce number of SWAP
APCSEE'14
11/9/14

9. Cost Increase Due to SWAP
Conventional approach: SWAP pairs
Original cost= 17  with swap= 35
APCSEE'14
11/9/14

10. Input line Order Impact
Input line ordering impact adjacency relationship
Will utilize this idea to find best order
Example:
Original  7 swap pairs
Rordered  1 swap pair
APCSEE'14
11/9/14

11. Problem Modeling Model target/control lines using interaction graph
Model input lines as set of linear processors
Formulation: Find best mapping of input lines to processor node to reduce overall circuit cost
Previously proposed  requires swap back (i.e. pairs)
APCSEE'14
11/9/14

12. New Local Heuristic
Extended algorithm to find best way to perform swap operation and avoid swap back
Example:
Moving control to target (eb), swap back immediately needed
Moving target to control (d  e), swap back avoided
APCSEE'14
11/9/14

13. Proposed Algorithm Apply HS algorithm to find input line assignment
For (i=1; i<= n; i++) {
- If gate(i) requires swap, then
- Find option that reduce # of swaps
- Insert swap with chosen direction }
APCSEE'14
11/9/14

14. Experimental Results Algorithm implemented in C++
Experiments run on PC, windows 7 OS, 3 GB RAM
RevLib benchmark were used
On Average:
Reduction of 67% compared to un-optimized circuit
Reduction of 53% compared to earlier work
APCSEE'14
11/9/14

15. SWAP Count Reduction on Benchmark Circuit
APCSEE'14
11/9/14

16. Conclusion
Proposed an extended version of HS algorithm to avoid swap pairs
The algorithm is very efficient and works very well for large circuits
It provided on average an enhancement of 53% over previously proposed algorithm
Future work is to extend the algorithm to include other cost metrics such as depth
APCSEE'14
11/9/14