1. Analog-to-Digital Converter
Module 3.B
Analog-to-Digital Converter
Tim Rogers 2017

2. Learning Outcome #3 A: Clocks and Real Time Interrupt (RTI)
“An ability to effectively utilize the wide variety of peripherals integrated into a contemporary microcontroller”
A: Clocks and Real Time Interrupt (RTI)
B: Analog-to-Digital Converter (ATD)
C: Serial Peripheral Interface (SPI)
D: Timer Module (TIM)
E: Pulse Width Modulation (PWM)
F: Serial Communications Interface (SCI)
How?

3. Learning Outcome #3 Why? “Analog to digital conversion”
The digital world is quantized and has fixed information size
On a macro scale, the real world is continuous and analog.
ATD

4. Analog Conversion Basics
If your reference voltages are 0V and 5V, and you have 2 bits to encode each sample, then the sampled voltage values possible are:
(A) 0, 2.5V
(B) 0V, 1.25V, 2.5V, 3.75V, 5V
(C) 0V, 1.25V, 2.5V, 3.75V 
(D) 1.25V, 2.5V, 3.75V, 5V
(E) 0V, 1.67V, 3.33V, 5V
If your reference voltages are 0V and 5V, and you have 2 bits to encode each sample, then the sampled voltage values possible are:
(A) 0, 2.5V
(B) 0V, 1.25V, 2.5V, 3.75V, 5V
(C) 0V, 1.25V, 2.5V, 3.75V
(D) 1.25V, 2.5V, 3.75V, 5V
(E) 0V, 1.67V, 3.33V, 5V
Analog Conversion Basics
Rate at which you take samples is called the sampling rate
Each reading of the analog signal is a sample
Each sample has a finite number of bits: quantization
Values always relative to a reference voltage. What you store is a fraction of the reference voltage.

5. Analog Conversion Basics
Design space for ATD converters involves picking the:
sample rate
# bits for quantization
encoder type
Analog Conversion Basics
Rate at which you take samples is called the sampling rate
Each reading of the analog signal is a sample
Goal: Reproduce the analog signal as faithfully as possible given constraints and acceptable error
Each sample has a finite number of bits: quantization
Actually reading the sample to find most appropriate value is called encoding
Values always relative to a reference voltage. What you store is a fraction of the reference voltage.

6. Determining an individual value (sampling)
One way to help narrow this sampling time is to use a “sample-and-hold” (S/H) circuit that acts as an ”analog memory”
S/H circuit will read in a voltage, then hold that value while the converter makes it binary
But in reality, converting the value to a digital value is not infinitely fast
Ideally, when we read in a voltage we do it infinitely fast

7. Setting the Sampling rate
If the highest frequency component of the input signal is Fi, what must your sampling frequency (Fs) be to ensure correct conversion?
(A) Fs=Fi
(B) Fs=Fi/2
(C) Fs=Fi*2
(D) Fs=Fi*4
(E) Fs=Fi/4
If the highest frequency component of the input signal is Fi, what must your sampling frequency (Fs) be to ensure correct conversion?
(A) Fs=Fi
(B) Fs=Fi/2
(C) Fs=Fi*2 
(D) Fs=Fi*4
(E) Fs=Fi/4
Key component of setting up an ATD is setting the sampling rate Ts
To do this – you need to do a spectral analysis of your input signal.
If the input signal has higher frequency components than Fs/2, you need to put a low-pass filter on the ATD input

8. If Fs (sampling frequency) = 20kHz an 11 kHz input signal (without any filtering) be encoded as:
(A) 10 kHz
(B) 11 kHz
(C) 9 kHz
(D) 21 kHz
(E) None of the above
If Fs (sampling frequency) = 20kHz an 11 kHz input signal (without any filtering) be encoded as:
(A) 10 kHz
(B) 11 kHz
(C) 9 kHz 
(D) 21 kHz
(E) None of the above
ATD Filtering
Q: What happens if you do not filter out the high frequency components?
A: Aliasing!
Original waveform
Alias reconstruction
In the frequency domain
Filter on ATD input referred to as anti-aliasing filter
Without a filter, frequencies are “folded back” into the baseband

9. Quantization
Number of bits for each sample: often called dynamic range
Quantization is the assignment of a fixed amplitude level (corresponding to an available binary code) to the incoming analog signal
Note that the converted code is relative to the reference voltage(s) applied to the converter (VRH = voltage reference high, VRL = voltage reference low)

10. Illustration of Quantization

11. Quantizing Intervals and Quantization Error
X Vrh
X Vrh

12. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

13. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

14. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

15. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

16. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

17. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

18. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

19. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

20. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

21. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

22. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

23. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

24. Scaling input analog voltage along x-axis
Quantizing Intervals and Quantization Error
Scaling input analog voltage along x-axis

25. Quantizing Intervals and Quantization Error

26. Quantizing Intervals and Quantization Error

27. Quantizing Intervals and Quantization Error

28. Quantizing Intervals and Quantization Error

29. Quantization noise Example: For n = 8,
This process introduces noise into your sample.
Signal to Quantizing Noise Ratio (SQNR) of a converter quantifies the amount of noise.
More Bits  Less Noise
SQNR = 20 log10 (2n / 1), where n is # of bit
This is derived from the general equation for a binary, pulse-code modulated communication channel
Example: For n = 8,
SQNRdB = 20 log10 (256 / 1)  48 dB
Solving for other values of n shows that the dynamic range is approximately 6 dB/bit

30. Analog Conversion Basics
Converter type
Wide variety of types, but two basic categories
Those requiring a DTA (digital-to-analog converter as an integral component)
Those not requiring a DTA
Successive approximation is one of the most common types of ATD converters integrated into microcontrollers
High resolution
Conversion time is a linear function of n
Based on “binary guess my number” game

38. 9S12C ATD Features and Modes
8 input channels
8/10-bit resolution, signed or unsigned
8 separate result registers
programmable sample time
fast conversion time (8 bits of accuracy in 9 µs)
may be program- or interrupt-driven
port PAD pins may also be used as general-purpose digital inputs (if ATD mode is not used)
conversion may be externally triggered

39. Reminder: Block Manual for 9S12 ATD

40. ATD Block Diagram Analog input channels 16-bit result registers
Reference high/low voltages
Analog input channels
Unused Port AD pins can be used as digital inputs
S/H “shutter speed” can be programmed

41. General ATD Operation Control registers (establish mode of operation)
1. Initialize
Control registers (establish mode of operation)
power up (overall enable)
initiate conversion on channel(s)
program-driven vs. interrupt driven mode
“shutter speed” (sampling aperture)
resolution (number of bits)
conversion sequence length (number of channels)
signed vs. unsigned result
analog vs. digital inputs

42. General ATD Operation Channel complete flag For an individual sample
2. Check Flags
Channel complete flag
For an individual sample
Sequence complete flag
The whole sequence is done
3. Read Results
When the conversion is complete – read the digital value.

43. Conversion Sequences Can sample 1 to 8 channels in a sequence
Both modes will set the sequence complete flag (SCF) when a sequence is done
Can sample 1 to 8 channels in a sequence
2 modes: scan and non-scan
Scan:
Read sequence – immediately restart
Non-scan:
Read sequence then stop
Used in Interrupt-driven mode.
Keeps interrupting every time done.
Used in Program-Driven (polling) mode.
Program initiates another scan when ready

44. Conversion Complete Flag (CCF)
After each individual channel is complete, the CCF flag is set
CCF for a given channel is automatically cleared when the result register for this channel is read

45. Initialing the conversion
You always have to setup a conversion sequence (even if it is just a sequence of one channel).
The ATD start conversing when the ATDCTL5 register is written to

46. ATD Features and Operating Modes
Reference voltages
VRH – reference high voltage
VRL – reference low voltage
minimum (either): -0.3v
maximum (either): +6.5v
Conversion range and resolution
If VRH = 5.0 v and VRL = 0.0 v, then an input voltage of 5.0 v will produce a converted output code of $FF, while an input voltage of 0.0 v will produce a converted output code of $00 (assuming unsigned mode)
Here, the resolution (or “step size”) of the converter is (VRH - VRL)/256 = v

47. ATD Features and Operating Modes
Conversion example:
If VRH = 5.0 v and VRL = 0.0 v, then an input voltage of 2.90 v will produce what converted output code?
Answer: / = 148 = $94

48. Interrupt when sequence complete Enable Bit
ATD Initialization
; Initializes ATD for program-driven operation
; STEP (1) Enable ATD for normal flag clear
; mode with interrupts disabled
atd_ini movb #$80,atdctl2
Bits 4-3:
External Trigger Mode
External Trigger bit
Interrupt Flag
Interrupt when sequence complete Enable Bit
Fast-Flag Clear Bit
Power on bit

49. Fast Flag Clear Mode AFFC (bit 6) – fast flag clear mode
Program driven mode:
Always should read the status first!
So “normal” mode fine.
AFFC (bit 6) – fast flag clear mode
“0” – normal CCF flag clearing mode (must read status register before reading result register to clear individual CCF)
“1” – fast CCF flag clearing mode (just reading the result register will clear CCF, i.e., do not need to read status register)
Interrupt driven mode:
If you are interrupt then you know the flag is set – reading it redundant.

50. External Trigger ATDCTL2 (control) ETRIGLE and ETRIGP (bits 4-3)
ETRIGE (bit 2)
“0” − disable external trigger
“1” − enable external trigger
Allows use of PAD7 to “trigger” an ATD conversion

51. Conversion sequence length
ATD Initialization
; Initializes ATD for program-driven operation
; STEP (1) Enable ATD for normal flag clear
; mode with interrupts disabled
atd_ini movb #$80,atdctl2
; STEP (2) Set the conversion sequence length to one
movb #$08,atdctl3
Bits 6-3:
Conversion sequence length
FIFO mode enable bit

52. Conversion Sequence Length
ATDCTL3 (control)
S8C, S4C, S2C, and SC1 (bits 6-3) – conversion sequence length
Out of reset – this is set to 4

53. FIFO Mode ATDCTL3 (control) FIFO (bit 2) – result register FIFO mode
“0” – non-FIFO mode (conversion results map into result registers based on the conversion sequence, starting with result register 0  “ADR0”)
“1” – FIFO mode (conversion results are placed in consecutive result registers between sequences)

54. ATD Initialization 0: 10bit mode, 1: 8-bit mode
; Initializes ATD for program-driven operation
; STEP (1) Enable ATD for normal flag clear
; mode with interrupts disabled
atd_ini movb #$80,atdctl2
; STEP (2) Set the conversion sequence length to one
movb #$08,atdctl3
; STEP (3) Select 8-bit resolution and nominal sample time
movb #$85,atdctl4
rts
0: 10bit mode, 1: 8-bit mode
Bits 4-0: Set ATD Clock
Bits 6-5: Sampling time
2 to 16 ATD clocks

55. Setting ATD Clock ATDCTL4 (control) PRS (bits 4-0) – clock pre-scalar
“00000” – divide by 2
“00001” – divide by 4
“00101” – divide by 12 (24/12 = 2 MHz)
“11111” – divide by 64
maximum bus clock frequency
maximum ATD clock frequency

56. ATD Conversion Timing CCFn set sample and transfer time
= 6 + final sample time*
*2/4/8/16 cycles
successive approximation conversion time
= 2 + number of bits
nominally 18 cycles for 8-bit resolution
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
write to ATDCTL5 starts conversion
SCF set if 4-ch mode
SCF set if 8-ch mode
Note: The SCF bit is cleared when a write to ATDCTL5 starts a new conversion (AFFC=0), or the first result register is read (AFFC=1)

57. Program-Driven Driver Function
; Channel number passed in B register
; Converted sample returned in A register
; STEP (1) Start conversion on desired channel
inatd andb #$07 ;mask unwanted bits
stab atdctl5 ;start conversion
;selected channel in
;“default” mode
Left or Right Justified Result.
0=left,1=right
Bit 2 to 0:
Channel to sample
Scan mode:
0=no-scan, 1=scan
Recall on ATDCTL3 we set the conversion sequence length. If MULT bit is 0, we sample the same channel multiple times
Signed/unsigned result
0=unsigned,1=signed
Multi-channel:
0-sample only one channel.
1 – sample over successive channels

58. Left Justified Signed/Unsigned Output Codes
Result Data Formats
Left Justified Signed/Unsigned Output Codes

60. Program-Driven Driver Function
; Channel number passed in B register
; Converted sample returned in A register
; STEP (1) Start conversion on desired channel
inatd andb #$07 ;mask unwanted bits
stab atdctl5 ;start conversion
;selected channel in
;“default” mode
; STEP (2) Wait for conversion sequence to finish
await brclr atdstat,$80,await
Bit 2 to 0:
Counter for # conversions complete
Sequence complete flag.
1=cconversion done
FIFO Overrun flag
External Trigger overrun Flag

61. Conversion complete flag for each result register
Other Status Register
Bit 7 to 0:
Conversion complete flag for each result register

62. Program-Driven Driver Function
; Channel number passed in B register
; Converted sample returned in A register
; STEP (1) Start conversion on desired channel
inatd andb #$07 ;mask unwanted bits
stab atdctl5 ;start conversion
;selected channel in
;“default” mode
; STEP (2) Wait for conversion sequence to finish
await brclr atdstat,$80,await
; STEP (3) Read result register and exit
ldaa adr0h ;(A)=(selected result)
rts

63. ATD Data Registers PORTAD (data input) register
In 8-bit, left aligned, non-FIFO mode, the first converted result will always be written to:
(A) ADR0H 
(B) ADR1H
(C) the result register corresponding to the converted channel
(D) the next available result register
(E) none of the above
In 8-bit, left aligned, non-FIFO mode, the first converted result will always be written to:
(A) ADR0H
(B) ADR1H
(C) the result register corresponding to the converted channel
(D) the next available result register
(E) none of the above
ATD Data Registers
PORTAD (data input) register
Returns digital value on Port AD pin if the corresponding ATDDIEN register bit is set to “1”
ADRxH (result, 16-bit) registers
ADR0H
ADR1H
ADR2H
ADR3H
– ADR4H
– ADR5H
– ADR6H
– ADR7H
We want the HIGH BYTE of the (2 byte) result because it is a BINARY FRACTION (the low byte would contain the two least significant bits, left justified, for the 10-bit conversion mode…this info would typically be used to ROUND the upper 8-bits of the result returned in the high byte)