1. A 3-bus implementation for the SRC
C bus
A bus
B bus R0 32
General Purpose Registers 32 32 32
A 3-bus implementation for the SRC
R31
All three buses are “Internal processor buses” IR PC
MAR
MBR
The register file must have 2 read ports and one write port A B
ALU
To External CPU Bus C

2. cannot use edge-triggered FFs to implement MAR as done before
Structural RTL for the sub instruction using the 3-bus data path implementation
Format: sub ra, rb, rc
Step
RTL T0
MAR←PC; MBR ← M[MAR], PC ← PC + 4; T1
IR ← MBR; T2
R[ra] ← R[rb] - R[rc];
Instruction Fetch
Instruction Execute
cannot use edge-triggered FFs to implement MAR as done before
At the end of each sequence, the timing step generator is initialized to T0

3. Review

4. CS501 Advanced Computer Architecture
Lecture17
Dr.Noor Muhammad Sheikh

5. Control Signals for the Fetch operation
Step
RTL
Control Signals T0
MAR←PC; MBR ← M[MAR], PC ← PC + 4;
PCout, INC4, LPC, LbMAR, MRead, T1
IR←MBR;
MBRout, C=B, LIR; T2
Instruction Execution

6. Structural RTL for the ld instruction
Step
RTL for ld T0
MAR←PC; MBR ← M[MAR], PC ← PC + 4; T1
IR←MBR; T2
MAR ←((rb=0):0,(rb!=0):R[rb]+ (16αIR<16> ©IR<15..0>),
MBR←M[MAR] T3
R[ra] ←MBR

7. Reset operation in SRC Hard Reset Soft Reset
The reset signal in SRC is assumed to be external and asynchronous.
Hard Reset
The SRC should perform a hard reset upon receiving a start (Strt) signal. This initializes the PC and the general registers.
Soft Reset
Soft reset results in initialization of PC only

8. Behavioral RTL for SRC Reset
The original behavioral RTL for
SRC without any reset operation
was
Instruction_interpretation:=( !Run&Strt: (Run  1,
Run: IR  M[PC],
PC  PC+4)
Instruction_execution:= (ld(:=op=1…);

9. Behavioral RTL for SRC Reset
The modified RTL after adding the
reset capability is
instruction_interpretation:=(! Run&Strt:(Run  1,
PC,R[0..31]  0),
Run&!Rst:(IR  M[PC],
PC  PC+4,instruction_exec),
Run&Rst:(Rst  0;PC  0);
instruction_interpretation)

10. Structural RTL for SRC Reset
Following modifications are required to add the
reset operation to the structural RTL for SRC
A check for the reset signal on each clock cycle
A control signal for clearing the PC
A control signal to load zero to control step counter

11. Example: The sub instruction with RESET processing
Step
RTN
Control Sequence TO
!Rst:(MA  PC,C  PC+4),
Rst:(Rst  0,PC  0,T  0)
!Rst:(PCout’ LMAR, INC4, LC’
MRead), Rst:(ClrPC, Goto0); T1
!Rst:(MD  M[MA]:PC  C),
Rst:(Rst  0:PC  0:T  0)
!Rst:(Cout’ LPC’ Wait),
Rst :(ClrPC, Goto0); T2
!Rst:(IR  MD),
Rst:(Rst  0: PC  0:T  0)
!Rst:(MBRout’ LIR),
Rst : (ClrPC, Goto0); T3
!Rst:(A  R[rb]),
Rst:(Rst  0: PC  0: T  0)
!Rst:(RBE, R2BUS, LA), T4
!Rst:(C  A - R[rc]),
!Rst:(RCE, R2BUS, SUB, LC), T5
!Rst:(R[ra]  C),
Rst:(Rst  0:PC  0: T  0)
!Rst:(LC’ RAE, BUS2R’ End),

12. Example: The sub instruction with RESET processing
Step
RTN
Control Sequence TO
!Rst:(MA  PC,C  PC+4),
Rst:(Rst  0,PC  0,T  0)
!Rst:(PCout’ LMAR, INC4, LC’
MRead), Rst:(ClrPC, Goto0); T1
!Rst:(MD  M[MA]:PC  C),
Rst:(Rst  0:PC  0:T  0)
!Rst:(Cout’ LPC’ Wait),
Rst (ClrPC, Goto0); T2
!Rst:(IR  MD),
Rst:(Rst  0: PC  0:T  0)
!Rst:(MBRout’ LIR),
Rst  (ClrPC, Goto0); T3
!Rst:(A  R[rb]),
Rst:(Rst  0: PC  0: T  0)
!Rst:(RBE, R2BUS, LA),
Rst : (ClrPC, Goto0); T4
!Rst:(C  A + R[rc]),
!Rst:(RCE, R2BUS, ADD, LC),
Rst :(ClrPC, Goto0); T5
!Rst:(R[ra]  C),
Rst:(Rst  0:PC  0: T  0)
!Rst:(LC’ RAE, BUS2R’ End),
Clears PC
Reset the
control Step
counter

13. Exception Processing A generalized exception handler should include
the following mechanisms
Logic to resolve priority conflicts
Identification of interrupting device
Saving the processor state
Exception disabling during critical operation
Saving the general purpose registers

14. Types of Exceptions Reset Exception
Reset operation is treated as an exception by some machines e.g. SPARC and MC68000.
Machine Check
This is an external exception caused by memory failure
Data Access Exception
This exception is generated by memory management unit to protect against illegal accesses.
Instruction Access Exception
Similar to data access exception
Alignment Exception
Generated to block misaligned data access

15. Types of Exception Program Exceptions Hardware Exceptions
Trace and debugging Exceptions
Nonmaskable Exceptions
Interrupts (External Exceptions)

16. Exceptions

17. 3-Bus Implementation

18. CS501 Advanced Computer Architecture