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IBIS Interconnect Task Group December 15, 2015

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Presentation on theme: "IBIS Interconnect Task Group December 15, 2015"— Presentation transcript:

1 IBIS Interconnect Task Group December 15, 2015
[Pin Pad Map] Proposal (Version 2) Bob Ross, Teraspeed Labs IBIS Interconnect Task Group December 15, 2015 Copyright 2015 Teraspeed Labs

2 GND Pin Only Example - Pin_rail and Pad_rail Terminals
[Pin Pad Map] keyword proposal Replaces [Bus Labels] and [Die Supply Pads] Equivalent information, without indirection confusion Not needed if pad_name not used [Begin Interconnect Model] used only to define terminals IBIS-ISS file or Touchstone file contains the electrical interconnection model information While the intended interconnect topology is shown, the actual topology and coupling depends on electrical contents that connect to the terminals Physical interconnection shown first Nine interconnection modeling cases Fewer terminal cases support simplified modeling extractions Copyright 2015 Teraspeed Labs

3 Legal Pin/Pad_rail Terminals
Terminal_Type / Qualifier  pin_name signal_name bus_label pad_name Aggressor Buffer_I/O X A Puref Pdref Pcref Gcref Extref Buffer_rail Y Pad_I/O Pad_rail Z Pin_I/O Pin_rail  Y X: I/O pin_names, Y,Z: POWER/GND names, Z: from [Pin Pad Map] A: Optional Aggressor column to assign one or more aggressor buffers Copyright 2015 Teraspeed Labs

4 Pad_rail to Bus_rail Connections
[Pin Pad Map] table used to illustrate Pad_rail to Bus_rail connections (Commented Lines are assumed to be the Bus_rail connections) Copyright 2015 Teraspeed Labs

5 Pin and pad association under [Pin Pad Map] keyword with [Pin] and [Pin Mapping]
Copyright 2015 Teraspeed Labs

6 pin_name and pad_name terminals for modeling physical interconnection
Copyright 2015 Teraspeed Labs

7 signal_name terminals for simplified interconnect model
Copyright 2015 Teraspeed Labs

8 bus_label terminals for higher resolution simplified electrical model
Copyright 2015 Teraspeed Labs

9 Terminals for modeling Pin_rail signal_name and Pad_rail bus_label interconnection
Copyright 2015 Teraspeed Labs

10 Remaining terminal selection options for electrical interconnect model extraction and simplification (some options may be impractical) Copyright 2015 Teraspeed Labs

11 Pad_rail to Buffer_rail Terminals
Connection terminals extended to Buffer_rail [Pin Mapping] is needed for connecting I/O buffer supplies to Buffer_rail terminals Direct Pad_rail to I/O buffer supply pins would use Pdref, Gcref (and possibly Puref, Pcref and Extref) terminals Six connection possibilities, although some may be impractical Pad_rail interface must be the same as Pin/Pad and Pad/Buffer terminal descriptions Copyright 2015 Teraspeed Labs

12 Legal Buffer/Pad_rail Terminals
Terminal_Type / Qualifier  pin_name signal_name bus_label pad_name Aggressor Buffer_I/O X A Puref Pdref Pcref Gcref Extref Buffer_rail Y Pad_I/O Pad_rail Z Pin_I/O Pin_rail  Y X: I/O pin_names, Y,Z: POWER/GND names, Z: from [Pin Pad Map] A: Optional Aggressor column to assign one or more aggressor buffers Copyright 2015 Teraspeed Labs

13 Pad_rail pad_name to on-die Buffer_rail signal_name terminals
Buffer_rail qualifiers Copyright 2015 Teraspeed Labs

14 Pad_rail pad_name to on-die Buffer_rail bus_label terminals
Buffer_rail qualifiers Copyright 2015 Teraspeed Labs

15 Pad_rail signal_name to on-die Buffer_rail signal_name terminals
Buffer_rail qualifiers Copyright 2015 Teraspeed Labs

16 Pad_rail bus_label to on-die Buffer_rail bus_label terminals
Buffer_rail qualifiers Copyright 2015 Teraspeed Labs

17 Pad_rail signal_name to on-die Buffer_rail bus_label terminals
Buffer_rail qualifiers Copyright 2015 Teraspeed Labs

18 Pad_rail bus_label to on-die Buffer_rail signal_name terminals
Buffer_rail qualifiers Copyright 2015 Teraspeed Labs

19 Comments [Pin Pad Map] keyword not needed if pad_name is not used
Pins and pads are merged during extraction However, documenting them may be informative [Pin] signal_name or [Pin Mapping] define Buffer_rail connections to Buffer_I/O supply terminals (Pdref, Gcref, Puref, Pcref, Extref) when using Buffer_rail Bus_label_signal_pin simplifies [Pin Mapping] and makes signal_name and bus_label qualifiers redundant and identical Copyright 2015 Teraspeed Labs

20 [Pin Pad Map] and [Die Supply Pads] Comparison
Copyright 2015 Teraspeed Labs

21 Trade-offs [Pin Pad Map] One less column
Less indirections since pin_name column gets signal_name from [Pin], or bus_label from [Pin Mapping] listings pin to pad mapping shows physical association (although some may be simplified since actual IBIS-ISS or Touchstone file describes interconnection) May require a few more lines for many pins to 1 pad cases [Die Supply Pads] Both signal_name and bus_label columns needed and be checked for consistency with [Pin] and [Pin Mapping] entries Pin_names for each pad_name must be found indirectly from [Pin Mapping] Hard to visualize the physical package association Copyright 2015 Teraspeed Labs

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