1. CPLD Product Applications
XC9500XL Architecture
CPLD Product Applications
TIB_archB1

3. XC9500XL Overview Superset of XC9500 CPLD Optimized for 3.3V systems
compatible levels with 5.0/2.5V
High fMAX = 200 MHz
Fast tPD = 4 nsec
Best ISP/JTAG support
Best pinlocking
Advanced Packaging
XC9500XL architecture is a further refinement of the XC9500 CPLD.
Careful thought has gone into providing the best complex programmable logic device to meet the needs of 3.3V systems - in a way that is also compatible with either 5 or 2.5V chips.
For today’s performance needs, this basically means state machine speeds up to 200 MHz, with combinational pin to pin delays as low as 4 nanoseconds on our fastest speed grade.
To complete the picture, the parts have been designed to give outstanding ISP and JTAG test support, while maintaining the XC9500 standard as the best pinlocking architecture.
Finally, to round things out, Xilinx has introduced several new packages - particularly the new Chip Scale Packages for maximum density in the best electrical environment.

4. Agenda Overview Technology Architecture ISP Electrical Compatibility
Support
Family

5. Features Each macrocell independently selects clock
source and phase inversion
Clock enable at each macrocell
Hysteresis on all inputs
Pullup/Bus Hold Option on Pins at power on
Expanded Function Block Inputs

6. Technology 0.35 micron FastFLASH technology 4 Layers of Metal
Optimized for high speed 3.3V systems
Ideal for ISP CPLDs
Reprogramming Endurance = 10,000
Charge Retention = 20 years
Critical to the success of today’s CPLDs is the underlying technology. Where others have chosen E2 technology,
Xilinx has pioneered the low voltage FLASH technology for a number of reasons. First, the smaller cell size permits the architecture to pack more control bits into a given area than E2. Second, almost all of the future nonvolatile memory production is becoming FLASH. This means more sources of process capacity and lower overall costs. In the CPLD world, smaller and lower voltage also translates to higher speed.
Smaller features, more metal and 3.3V all mean speed.
As well as speed, these parts are specifically targeted for robust ISP. In particular, high endurance long charge retention ISP. It’s in the numbers!

7. Flash vs E2 Endurance Flash delivers: - highest quality
- no speed degradation
- 20 year retention
- reliable reprogramming
- worry free field upgrade

8. Architecture Uniform Identical Function Blocks Identical Macrocells
Identical I/O pins
Abundant Global/Product Term Resources
Great synthesis results
Best pinlocking results
These bullets highlight the architectural features that underly the XC9500XL architecture philosophy. Key to design is simply remembering that the architecture is uniform - Function Blocks, Macrocells, I/O pins and Global/Product Term Resources.
This uniformity makes the software job of efficient synthesis much easier than if the architecture were a set of special cases.
Additionally, this uniformity also dramatically aids in producing great pin-locking results.

9. CPLDs
XC9500XL devices are similar to having multiple PAL devices interconnected in one chip
Best applications
Wide functions
Complex counters
Complex state machines
PAL/GAL or TTL integration
Non-volatile
BUS Interface/Control
PAL
Swi-
tch
Mat-
rix
PAL
PAL
PAL
Prog.
AND
array
Fixed OR
array
FF/
Macro-
cell
FF/
Macro-
cell

10. High Level Architecture

11. FastCONNECT II Switch Matrix
Very High Speed Switch Matrix
Greater connectability for all signals
High routability at high utilization
Software delivers high speed automatically
Substantial power reduction
Key to high speed on XC9500XL designs is the new FastCONNECT II Switch Matrix. This structure is a substantially expanded very high speed multiplexer.
Many designs that had difficulty fitting in the XC9500 family - one of the industry’s best - easily fit into the XC9500XL, even at very high utilization. The software efficiently manages the signals to deliver very high speed connections with minimum effort.
As an extra, this structure substantially reduces the power dissipation associated with earlier interconnect structures.

12. Function Block
54 Inputs Highest FB Fanin

13. Macrocell

14. Product Term Allocation
3 available here
2 p-terms required here
5 available here
5 native p-terms
Total = 18
requires 2 X tpta delay
added to tPD
5 available here

15. Industry’s Best Pin-Locking
Product Term Allocator allows any product term to be borrowed by any macrocell in the same function block
Product Term Allocator allows for timing to be held for small to medium logic changes
Footprint compatibility allows for easy migration to larger or smaller devices using the same device package

16. Why Pin-Locking is Necessary
The major advantages of In System Programming can only be realized with field-upgrades
It does not make sense to do field upgrades if the board needs to be re-worked for minor logic changes
It does not make sense to do field upgrades if timing cannot be met

17. Pin Locking vs Pin Preassignment
The software should be allowed to make first pass pin assignments
Pre-assigning pins can lead to timing and density underutilization

18. ISP Original XC9500 JTAG and ISP instructions: New instruction:
Program Erase Verify Blankcheck
ID Code Usercode
Intest Extest Hi-Z Bypass
New instruction:
CLAMP
permits pin by pin definition of logic level during bypass
Added S/W support with XACT M1.5
CPLD and FPGA download via JTAG

19. Bus Hold Logic
A weak latch holds last state on I/O
RBH= 50kOhms

20. Bus Hold Logic Two modes of operation
User mode: Holds last state
ISP or blank device: pull-up resistor
Better than just a pull-up resistor
eliminates slow changing of bus signals during hi-z
reduced system power during hi-z

21. Voltage Compatibility
VCCINT = 3.3V
VCCIO = 3.3V/2.5V
CORE
LOGIC
Note: output p-channel gives full rail swing

22. Voltage Compatibility 3.3/5V
VCCIO
VCCINT 5V
3.3V
Any
Any
XC9500XL
3.3V
5V TTL
3.3V
3.3V
device
device

23. Voltage Compatibility 3.3V/2.5V
VCCIO
VCCINT
3.3V
2.5V
Any
Any
3.3V
XC9500XL
2.5V
2.5V
2.5V
device
device

24. XC9500XL Voltage Compatibility Summary
 EIA Standard Voltage Levels
 No Power Supply Sequencing Restriction

25. Input Signal Hysteresis
VOH
50 mV
VOUT
(VOLTS)
VOL
1.45V
1.40V
VIN
(VOLTS)

26. Power Optimization Minimum of 67% decrease in power over 5V CPLDs
Low power option per macrocell
Even lower power if I/Os swing 0-2.5V
FastCONNECT II lower power than XC9500
I/Os swing full VCCIO range with p-channel pullups (shuts off attached external logic)

27. XC9500XL Design Software
XC9500XL Fitters in all Xilinx Standard S/W Packages
Foundation M1.5
Alliance M1.5
Support for Schematics, Verilog, VHDL, Abel
Exemplar
Synopsys
Synplicity
more
XC9500XL is supported not only by the same design software that supports XC9500 CPLDs, but also by the same software that supports the Xilinx FPGA product line.
This includes both Foundation and Alliance software packages from Xilinx. As well, it includes a large group of third party providers of HDL and simulation software, along with the usual schematic providers for both PCs and workstations.

28. Programming Flexibility
Mount XC9500/XL device to PCB, fixing pinouts
Program via download cable (no programmer required)
Recompile design, erase & reprogram multiple times
Debug logic with extended JTAG test
XC9500/XL advantages
Pin-locking architecture maintains pinouts
Endurance of 10,000 cycles
Extended JTAG test
XC9500
ISP
Download Cable

29. Expanded Manufacturing Capability
Mount XC9500/XL and program using standard manufacturing automatic test equipment and JTAG
Board test using IEEE compliant JTAG
Implement last-minute design changes
XC9500/XL advantages
Fast program time (~1 second XC95144XL) using Automated Test Equipment (ATE)
Excellent pin-locking for last-minute design changes
Complete IEEE JTAG

30. Third Party ATE Support
Hewlett-Packard
Teradyne
Gen-RAD
Common Support for both Xilinx FPGAs and CPLDs.

31. XC9500XL Family

32. XC9500XL Conclusion is the CPLD family that meets
your leading-edge system needs