1. USB Pixel 3D System Update I-Beam Simulation
Loc Hua
Jimin Kim

2. Theory Simulation Experiment Overall Project
Combine theory, simulation and experiment
Design and build USB Pixel 3D detector for ATLAS
Simulate detector geometry
Optimize experiments

3. Goals Set up USB Pix Software Build USB Pix Hardware
Test Experimental Properties
Report to Collaborators
Build Simulation
Experiment
Build simulation
Predictive power
Geometry of detector
Report to Collaborators
Experimental work

4. Goals Set up USB Pix Software Build USB Pix Hardware
Test Experimental Properties
Report to Collaborators
Build Simulation
Experiment
Within one week
Set up USB Pixel software
Set up USB Pixel hardware

5. Goals Set up USB Pix Software Build USB Pix Hardware
Test Experimental Properties
Report to Collaborators
Build Simulation
Experiment
Within one week
Set up USB Pixel software
Set up USB Pixel hardware
By end of quarter
Initial measurements
Begin writing simulation

6. Goals Set up USB Pix Software Build USB Pix Hardware
Test Experimental Properties
Report to Collaborators
Build Simulation
Experiment
Within one week
Set up USB Pixel software
Set up USB Pixel hardware
By end of quarter
Initial measurements
Begin writing simulation
Next quarter
Gather necessary properties of detector
Test simulation

7. Goals Set up USB Pix Software Build USB Pix Hardware
Test Experimental Properties
Report to Collaborators
Build Simulation
Experiment
Within one week
Set up USB Pixel software
Set up USB Pixel hardware
By end of quarter
Initial measurements
Begin writing simulation
Next quarter
Gather necessary properties of detector
Test simulation
By end of next quarter
Run experiments

8. USB Pixel 3D

9. USB Pixel 3D

10. USB Pixel 3D

11. USB PixBoard - Specs Multi-IO USB/FPGA Board
15 Mbyte/Sec FPGA – PC date transmission speed
2 Mbyte SRAM
Xilinx XC3S1000 FPGA
LVDS and TTL IOs (for ext. trigger, TDC etc.)
8051 USB microcontroller
Drivers for Windows XP and Linux
Module Adapter Card
Four channels support single chip cards or modules
Serial powering option for modules
Current and (individual) voltage measurement for SP
“Lightweight”/low-cost replacement for TPLL/TPCC
Limited FPGA/memory resources
No DSP
No dedicated, programmable delay lines

12. I-Beam Simulation