1. Lecture 2 Boolean Algebra Basic
An algebra A is a mathematics theory involving a set of elements S and a set of operations O that act on the members of S.
The smallest Boolean algebra contains two values, 0 and 1.
If X is a Boolean variable, then either X = 0 or X = 1.
1 can mean high voltage or True while 0 might correspond to low voltage or False.
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2. Basic Operations NOT (Complement, inversion) X X’ X’ 1 1 X Truth table1 1 X
Truth table
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3. Basic Operations-cont.
AND (Boolean multiplication) A B
A.B (AB)
A B AB
0 0
0 1
1 0
1 1 A B 1
Open: 0
Close: 1
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4. Basic Operations-cont.
OR (Boolean addition, inclusive OR) A B
A+B
A B
A + B
0 0
0 1
1 0
1 1 A 1 B
Open: 0
Close: 1
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5. Boolean Expressions Expressions Examples: Operation order: AB’ + C (1)
[A(C+ D)]’ + BC (2)
Each expression corresponds to a network of logic gates.
Exercise: Draw the logic gate network for (1) and (2).
In (2), there are 4 variables and 5 literals.
Operation order:
Parenthesis, NOT-> AND-> OR
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6. Literals and Truth Table
When an expression is realized using logic gates, each literal in the expression corresponds to a gate input.
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7. Literals and Truth Table
Specify the values of the variables in the expression.
n variables have 2n different combinations of values of the variables.
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8. Basic Theorems Operation with 0 and 1 Idempotent laws Involution law
X + 0 = X
X + 1 = 1
X‧1 = X
X‧0 = 0
Idempotent laws
X + X = X
X‧X = X
Involution law
(X’)’ = X
Laws of complementarity
X + X’ = 1
X‧X’ = 0
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9. Basic Theorems-cont. Commutative laws Associative laws
X + Y = Y + X
XY = YX
Associative laws
(X+Y) + Z = X + (Y + Z) = X + Y + Z
(XY)Z = X(YZ) = XYZ
Distributive laws
X(Y + Z) = XY + XZ
X + YZ = (X+Y)(X+Z)
Proof: (x+y)(x+z) = x (x+z) + y(x+z) = xx + xz + yx + yz = x + xz + xy + yz = x.1 + xz + xy + yz = x(1+z+y) + yz = x .1 + yz = x +yz
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10. Basic Theorems-cont. Simplification theorems Example: Simplification
XY + XY’ = X
(X+Y)(X+Y’) = X
X + XY = X
X(X+Y) = X
(X+Y’)Y = XY
XY’ + Y = X + Y
Example: Simplification
Z = (AB+C)(B’D+C’E’) + (AB+C)’= (AB+C)’ + B’D+C’E’
Proof y + xy’ = (y+x)(y+y’) = (y+x)1 = y+x
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11. Basic Theorems-cont. Theorem for multiplying out and factoring
Use distributive law.
(X+Y)(X+Z) = X +YZ
Example: (A+BC)(A+D+E)
= A + BC(D+E) = A +BCD +BCE.
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12. Proof of Theorem or Law Using truth table Using algebra manipulation
Associative law
(A+B) + C = A + B + C
What is the difference?
# of fan-in
Potential speedup
Using algebra manipulation
A +A = A
Using Principle of Duality
Principle of duality: Any theorem or identity in switching algebra remains true if 0 and 1 are swapped and,．and + are swapped.
Example: If X + XY = X．1, then
X．(X+Y) = X + 0 = X
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13. Some Properties
In Boolean algebra, AND (OR) operation distributes over OR(AND).
X(Y+Z) = XY + XZ
A+BC = (A+B)(A+C)
Application of simplification
Example: (A + B’C + D + EF)(A+B’C+ (D+EF)’);
View A+B’C = X, D + EF = Y; so this is (X+Y )(X+Y’) = X
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14. SOP
An expression is said to be in sum of products form when all products are products of single variables only. Use frequently.
Example
A’B + CD’E + AC’E’ Yes.
(A+B)CD + EF No.
ACD +BCD +EF Yes.
Use Multiplying out to get SOP
(A+BC)(A+D+E) =
A + BC(D+E) = A + BCD +DCE.
Using (X+Y)(X+Z) = X + YZ
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15. POS
An expression is said to be in product of sums form when all sums are sums of a single variable. Not use as often as SOP form in industry.
Example
(A+B’)(C+D’+E) Yes.
(A+B’)(C+D’+E)F Yes.
(A+B)(C+D) + EF No.
Use Factoring to get POS
A + B’CD = (A + B’) (A+ CD); first factoring.
= (A+B’)(A+C)(A+D); second factoring.
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16. Typical IC Design Flow System spec RTL
HDL: Hardware Description Language
Verilog
Schematic capture
DESIGN ENTRY
Design correct?
Functional simulation No
Yes
Synthesis
Physical design
Tape-out
Timing requirements met?
Timing/Power
simulation
System spec
C/C++
model
RTL
FPGA prototyping
Post-layout simulation

17. To produce an IC HDL C, C++
DRC: design rule check: ensures that the physical layout of a particular chip  satisfies a series of recommended parameters called Design Rules. 
LVS: Layout Versus Schematic (LVS) 
ERC: electrical rule check…..

18. Describe a circuit in a form of module Gate Level
module mux (x1, x2, s, f);
input x1, x2, s;
output f;
not (si,s);
and (u, si, x1);
and (l, s, x2);
or (f, u, l);
endmodule
keyword u l
output
Alternatively
and (u, ~s, x1); // without an explicit not ahead

19. Behavioral: logic equation (functional expression)
Continuous assignment:
f is re-evaluated whenever
the right hand side
signal changes.
module mux (x1, x2, s, f);
input x1, x2, s;
output f;
assign f = (~s & x1) | (s &x2);
assign y = f | x2;
endmodule
No order for f and y,
concurrent statement;
assign: for nets (like wire) since nets can not
hold values, so you need to assign the
value continuously.

20. Behavioral: procedural statement
Values inside a always block must retain their values until any change of signals in the sensitivity list. To hold on the values, use reg to keep them.
module mux (x1, x2, s, f);
input x1, x2, s;
output f;
reg f;
or x2 or s)
if (s == 0)
f = x1;
else
f = x2;
endmodule
list)
Evaluated in the order
given by the code;
if first, then else.
= blocking assignment
(evaluated in order)

21. More compact procedural statement
module mux (input x1, x2, s, output reg f);
x2,s)
if (s == 0)
f = x1;
else
f = x2;
endmodule

22. Coding in 3 ways: Gate instantiation Continuous assignment (assign)
Procedural statements (always)
Blocking assignment = sequencing
S = X + Y;
C = S[0]; // C takes the new value from X+Y.
Non-blocking assignment <=
S <= X + Y;
C <= S[0]; // at simulation time ti, C takes the value of S[0] at simulation time ti-1