1. NxN Crossbar design for Barrel Shifter
Tri-state
buffer
Decoder x0 x2 x1 y0 y2 y1
Shift
count
X-input
Y-output …
Decoder selects the shift amount
Number of gates: O(N2)
Delay: O(1) …

2. Shift and Rotate Hardware

3. Review

4. CS501 Advanced Computer Architecture
Lecture 36
Dr.Noor Muhammad Sheikh

5. Logarithmic Barrel Shifter
A shift/bypass
cell
Shift Count
Input
Word
Output
Bypass/Shift 1 bit right
Bypass/Shift 2 bit right
Bypass/Shift 4 bit right
Bypass/Shift 8 bit right
Bypass/Shift 16 bit right
Number of gates: O(NlogN)
Delay: O(logN)

6. Block diagram of an ALU MUX MUX Shifter x Logic Z Y CONTROL Condition
Shift count
Shifter
Condition
codes
MUX n x
MUX
Logic Z n Y n
CONTROL
Arithmetic
OPCODE

7. Floating-point representation
Floating-point numbers have two parts
The Significand
The Exponent
e.g. consider the number
-5.7x10-3
The
Exponent
Sign is negative
The Significand or Mantissa
Base is 10; fixed for a given representation

8. Floating-Point Representation
A common layout for floating-point number is
sign
exponent
fraction s e f 1 me mf
M bits
The Bias or excess representation
s=1floating point numbers negative
s=0floating point number is positive
me = number of bits in exponent field
mf = number of bits in fraction field
Value(s,e,f) = (-1)s x f x 2e

9. Continued
Floating point numbers are generally represented by sign and magnitude form.
Exponent could be represented in the form of 2’s complement, but it gives some complications, e.g. complications in case of sorting algorithms.
The solution to the complications is biased representation.

10. Floating-point representation
Bias representation
In bias, or excess representation, a number is added to the exponent so that the result is always positive
Biased representation is useful for normalized numbers
Instead of bias, two’s complement form can also be used to represent the exponent

11. IEEE 32 bit single precision format
f1f2…f23
sign
exponent
fraction 31 1 8 9
Fraction bits of significand including the hidden bit
Positive values between 0 to 255 with bias=127
The IEEE standard floating point numbers can be either
nomalized or denormalized. The denormalized number
does not have a hidden bit

12. Types and values represented by IEEE Single-precision format
255
none
NaN
254
127
(-1)sx(1.f1.f2…)x2127
Normalized … 2
-125
(-1)sx(1.f1.f2…)x2-125 1
-126
(-1)sx(1.f1.f2…)x2-126
-127
Denormalized

13. Range of possible numbers
Positive underflow
0 to (0.5 x )
Negative underflow
(-0.5 x ) to 0

14. Floating point Addition and Subtraction
The steps taken in floating point
addition or subtraction are
Unpacking of sign, exponent and fraction fields
Alignment of significant
Addition or subtraction operation
Adjusting for carry
Rounding off the result
Overflow checking and packing

15. Floating Point Addition,
Binary :
0.510 = 1/210= 0.12= x 2-1
= -7/1610 = -7/24= = x 2-2
Align: x 2-2 → x 2-1
Addition: x ( x 2-1) = x 2-1
Normalization of Sum:
X 2-1 = x 2-2
= x 2-4

16. Floating point Add/Sub Hardware
Exponent
Subtractor
Swap
Alignment
Shifter
Significand
Adder/sub
Normalize
and round
Lead zero
counter
Subtract and
bias
select
Sign
computation e1 e2 f1 f2 s1 s2
FA/FS er sr fr
For alignment
And
normalization

17. Floating Point Multiplication and Division
The floating point multiply procedure is as follows
Unpack sign, exponent
and significands
Apply xor operation to
signs, add exponents,
Multiply significands
Normalize, round
And shift
Adjust for
overflow
Pack the result
and report exceptions

18. Floating Point Multiplication and Division
The floating point divide procedure is as follows
Unpack sign, exponent
and significands
Apply xor operation to
signs, subtract
exponents,
divide significands
Normalize, round
And shift
Adjust for
overflow
Pack the result
and report exceptions