CE 454 Computer Architecture

CE 454 Computer Architecture
Lecture 7 Ahmed Ezzat The Microarchitecture Level, Ch-4.1, 4.2, 4.3

Outline Microarchitecture Overview IJVM
Data Path Microinstructions Microinstruction Control: The Mic-1 IJVM Stacks Memory Model Instruction Set Compiling Java to IJVM Example Microinstructions and Notation Implementation of IJVM Using the Mic-1 Reading Assignment: Simulation documentation CE 454 Ahmed Ezzat

Microarchitecture Overview
Microarchitecture is the next-level up above the digital logic. It implements the ISA (Instruction Set Architecture), which is the level above it Our chosen ISA is a subset of JVM – only Integer instructions and hence IJVM This level is a micro-program that will execute IJVM instructions Micro-program has simple instructions and state (values assigned to variables) State changes as code executes Machine runs in a fetch-execute loop Fetches instruction (opcode =operation code) Fetches operands (data) Executes CE 454 Ahmed Ezzat

Microarchitecture Overview: Data Path
Part of the CPU containing ALU, its inputs and outputs Some registers have symbolic names MAR, MDR, PC, etc. CE 454 Ahmed Ezzat

Notations These registers are accessible only at the microarchitecture level Registers can write data into gray B bus C bus writes data into registers Light arrows exchange data with memory CE 454 Ahmed Ezzat

Operations Operands to ALU come from register H and bus B Note: H is written as output from Shifter – output from previous ALU operation Six control lines for ALU, one for Shift control CE 454 Ahmed Ezzat

Control Signals to ALU Not all of these are needed for our IJVM ENA, ENB –enable A, B INVA –invert A, INC – increase by 1 Can load ALU, pass the data through Shifter and store it in H in the same cycle. CE 454 Ahmed Ezzat

Data Path Timing Have four sub-cycles (implicit) in a clock cycle Control signal setup (Δw) Load register into B-bus (Δx) ALU & shifter op (Δy) Result back to registers along C bus (Δz) CE 454 Ahmed Ezzat

Data Path Timing Starts with falling edge of clock Ends with rising edge of clock (Clock cycle) > (Δw + Δx + Δy + Δz) CE 454 Ahmed Ezzat

Memory Operations Have 32 bit word-addressable port and 8 bit byte addressable port (controlled by PC) MAR, MBR, PC are registers MBR can only output data to bus B in two formats CE 454 Ahmed Ezzat

Memory Operations MBR, MAR, PC driven by control signals MAR, H does not have enable signals -always on MAR has word addresses, PC has byte addresses Resulting memory fetch will be put into low order 8 bits of MBR PC/MBR is used to read instructions (executable byte stream). All,other registers use words MAR/MDR used to read operands (word boundary) PC = 2 memory reads, out byte-2 MAR = 2 memory reads, out bytes 8-11(word-2 which is 4 bytes) Output of MBR gated to bus B CE 454 Ahmed Ezzat

Output Formats of MDR 8-bit Unsigned Values: Used for indexes or part of 16 bit integers Put into low 8 bits in bus B Zeros in upper 24 bits Signed value between –127 and +127: Copy MBR sign bit (leftmost 8) into 24 leftmost bits Put numerical value into 8 rightmost bits (known as sign extension) That is why there are two lines from MBR to B CE 454 Ahmed Ezzat

Need 29 Signals 9 to write from C bus into registers 9 to write to B bus for ALU input 8 to control ALU and shifters functions 2 to indicate r/w to MAR/MDR 1 for memory fetch via PC/MBR CE 454 Ahmed Ezzat

Microarchitecture Overview: Microinstructions
Cycle = Gating values on to B Propagating values through ALU and shifters Driving signals on to C bus Writing results in registers If memory r/w asserted, initiate action Memory operation started at end of cycle Data available only after next cycle. (one cycle missed!) May write value in C onto more than one register, but never put value onto B from more than one register CE 454 Ahmed Ezzat

Microinstructions Formats To select inputs to B bus need 4-bits (2**4=16), only 9 are needed Bits needed for controlling data path = = 24-bits for one cycle NEXT_ADDRESS and JAM needed to indicate next instruction to be fetched CE 454 Ahmed Ezzat

Microinstructions Formats Addr: potential next address JAM how next microinstruction is selected C: Which register written from C Mem: memory function B: Source of B CE 454 Ahmed Ezzat

Microarchitecture Overview: Microinstructions Control – The Mic-1
Sequencer steps through operations to execute each ISA instruction providing. Produces every cycle the following: State of each control signal (asserted or not) Address of next instruction Control Store = holds microprogram, made of read only memory (logic gates) Example control store contain 512, 36 bit words Each microinstruction specifies its successor Needs own counter = MPC (Microprogram counter) Memory data register = MIR (Microinstruction register) CE 454 Ahmed Ezzat

Microarchitecture Overview: Microinstructions Control: The Mic-1
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MPC, MIR “B” 4-bits drives 4 to16 decoder to determine what goes on B bus Steps (sub-cycles): At falling edge MIR loaded from word in control store pointed by MPC (s-Cycle 1) Signals propagate to data paths and register put onto bus B ALU knows operation (s-Cycle 2) CE 454 Ahmed Ezzat

MPC, MIR Steps (Contd.): ALU, N, Z stable output in s-Cycle 3 Output propagates to register via C bus Registers, N, Z loaded in s-Cycle 4 CE 454 Ahmed Ezzat

Determining Next Microinstruction Starts when MIR is stable NEXT-ADDRESS copied to MPC If JAM is 000 nothing more is done Else If JAMN is set, N-bit is ORed to higher order bit of MPC If JAMZ is set, Z-bit is ORed to higher order bit of MPC Why? Because after rising edge of clock bus B outputs are no longer valid: ALU outputs not reliable, hence save status in N and Z CE 454 Ahmed Ezzat

Determining Next Microinstruction High Bit set Boolean Function computed in Logic Gate = (JAMZ and Z) or (JAMN and N) or NEXT_ADDRESS[8] MPC takes either of: NEXT_ADDRESS NEST_ADDRESS with higher order bit Ored with 1 If high-order bit of NEXT_ADDRESS is 1, JAMN and JAMZ are not relevant CE 454 Ahmed Ezzat

Determining Next Instruction: Example Current 0x75 has NEXT_ADDRESS = 0X92. If Z bit is 0, next instruction = 0x92, else 0x192 CE 454 Ahmed Ezzat

Using MBR for Next Address Computation If JMPC set, 8 MBR bits bitwise Ored with 8 low order bits of NEXT_ADDRESS field When JMPC is 1, 8 low order bits of NEXT_ADDRESS is zero, higher order is 0 or 1 So NEXT_ADDRESS becomes 0x000 or 0x100 If JMPC is zero, passes NEXT_ADDRESS to MPC as is Allows multi-way branching (jump), MBR has opcode CE 454 Ahmed Ezzat

How Microinstructions Work: Summary SubCycle 1: MIR loaded from address in MPC SubCycle 2: MIR propagated out, B loaded SubCycle 3: ALU, Shifter produce stable value SubCycle 4: C, Memory and ALU stable Registers loaded from C N, Z loaded MBR, MDR get values from memory (If started in previous cycle) MPC gets value New cycle begins CE 454 Ahmed Ezzat

An Example ISA: IJVM Stacks
IJVM: Integer Java Virtual Machine Stacks: Used to implement procedures Stack frames are used to store: Local variables (environment) Temporary results of arithmetic computations LV bottom, SP top of stack. Base+offset addressing CE 454 Ahmed Ezzat

An Example ISA: IJVM Stacks
Operand Stacks for Arithmetic Stacks are rarely used for arithmetic operations Could be mixed in with local variable stack CE 454 Ahmed Ezzat

An Example ISA: IJVM The IJVM Memory Model
Memory = 4GB = 1 GB array of 4 byte words Unlike most ISA, JVM does not make addresses visible at the ISA level. Instead ISA instruction index based on a base address. 4 Separate areas of memory are defined: Constant Pools (CPP): Contain constants, strings, and pointers to other areas Cannot be written by an IJVM program. Loaded when program is bought into memory CPP is an implicit register that points to the beginning address Local Variables (LV): For each method (function, procedure) there is a frame (local variable frame) Beginning has (in and out) parameters LV is the beginning of Local Variable stack CE 454 Ahmed Ezzat

Contd. Operand Stack (SP) Not to exceed a certain size, computed at Java compile time Directly above LV stack. SP indicate top/end of the stack Method Area Text area of code reside here – treated as byte array PC points to an address containing the next instruction to be fetched. All addresses (CPP, LV, SP) refer to words (4 byte), except PC refers to bytes E.g.: LV+4 refers to 4th word after LV. E.g.: PC +1 refer to next byte after PC CE 454 Ahmed Ezzat

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An Example ISA: IJVM The IJVM Instruction Set
IJVM Assembly Instructions (Macroarchitecture) Instructions consists of an opcode and optional operands, encoded in Hex Instructions work as: Push words onto stack from various sources Constant pool: LDC_W Local variable frame: ILOAD Instruction set: BIPUSH Compute Pop words and store in local variable frame ISTORE CE 454 Ahmed Ezzat

CE 454 Ahmed Ezzat

IJVM Assembly Instructions Some instructions come in various forms, IJVM will support: Long general format Frequently used short format Two Arithmetic operations: IADD, ISUB Two Logical Operations: IAND, IOR 4 Branch Operations: offset follows opcode GOTO, IFEQ, IFLT, IF_ICMPEQ CE 454 Ahmed Ezzat

Call and Return Instructions INVOKEVIRTUAL Invokes another method Caller pushes callee address onto stack OBJREF Caller pushes in parameters onto stack INVOKEVIRTUAL is executed IJVM limitation: method can invoke a method existing within its own object, i.e., address of called procedure is determined by the CALL instruction IRETURN Returns to caller or return from callee CE 454 Ahmed Ezzat

IJNVOKEVIRTUAL CE 454 Ahmed Ezzat

Format of Method Disp in INVOKEVIRTUAL points to constant pool location that has the method address First word (4 bytes) in method has special data First two bytes Have # of parameters, with OBJREF counted as parameter 0 LV points to OBJREF (parameter 0) Last two bytes Size of local variable area of the method being invoked Needed to allocate stack for new call Finally 5th byte has first opcode to be executed CE 454 Ahmed Ezzat

INVOKEVIRTUAL Execution Compute # of parameters (I.e., parameter 0 is the OBJREF) using the first 2-bytes in the method area Compute base address of new stack using the second 2-bytes (procedure local variable size) in the method area Set LV to OBJREF. Then erase value there and put address at end of stack (increase by size of stack) At this location put old PC, next put Callers LV, and reset SP to this address (I.e., callers LV is top-of-stack) Set PC to 5th byte in method code, i.e., opcode to first instruction to be executed CE 454 Ahmed Ezzat

IRETURN CE 454 Ahmed Ezzat

Executing IRETURN Reverse INVOKEVIRTUAL instruction De allocate space for this stack frame Return value is placed at top of stack Use link pointer to restore PC and LV of the callee respectively SP is set to point to the return value location In the next cycle, go back to instruction after the call in callee. No explicit I/O in IJVM, they are done by special methods which perform the I/O CE 454 Ahmed Ezzat

An Example ISA: IJVM Compiling Java to IJVM
CE 454 Ahmed Ezzat

An Example ISA: IJVM Compiling Java to IJVM
Operand Stack Local variables are (i, j, k) in that order Horizontal line: empty stack CE 454 Ahmed Ezzat

An Example IJVM Implementation: Microinstructions and Notations
Use Higher level syntax (MAL – Micro Assembly Language) to indicate micro-program operations, i.e., instead of describing the control store in binary (36-bits per word). MAL reflects the microarchitecture Each instruction can be executed in one cycle (4 sub-cycles) During one cycle: any register can be written (typically one). Only one register can be gated to the B bus The A bus side of the ALU can have only +1, 0, -1, Register H Example: MDR = H + SP Load SP to B Load H and B to ALU and add them Store the result back in MDR CE 454 Ahmed Ezzat

Be Careful: MDR = SP + MDR is not legal as it needs more than one cycle So is H = H - MDR as subtrahend must be in H We extend our notations to include multiple equal signs SP = MDR = SP + 1 Memory read write indicated by rd, wr, WSP Reads and writes happen in 4 byte words through 4-byte words using MAR/MDR, and indicated using rd and wr Reads and writes of 1 byte using PC/MBR, and indicated using fetch as the opcode Both kinds of memory operations can proceed concurrently One register can’t received data from memory and data path in same cycle MAR = SP; rd //set MAR to SP and initiate rd operation into MDR MDR = H // set MDR to H At the second cycle we have conflict! CE 454 Ahmed Ezzat

Legal Instructions CE 454 Ahmed Ezzat

Microinstructions: Addressing Each instruction explicitly supplies the next instruction’s address Explicit jumps given by goto Label Data path is available during a goto instruction; typically every line should have goto, except when target is the next line, it may be omitted Additional notations for branches: Extend MAL to support 2 New registers N, Z Z = TOS // runs TOS through ALU and set the Z & N flip-flops Notation for setting the JAMZ bit is If (Z) goto L1; else goto L2 Z = TOS; if (Z) goto L1; else goto L2 Hardware requires that L1 and L2 have same low-order 8-bits (NEXT_ADDRESS is 9-bits), i.e., L1 = L CE 454 Ahmed Ezzat

Microinstructions: Addressing Notation to set JMPC bit Goto (MBR OR Value) Use value for NEXT_ADDRESS and set JMPC bit to enable ORing MBR (low-order 8-bits) with NEXT_ADDRESS into MPC. If value = 0, it is sufficient to write Goto (MBR) Figure 4-17 gives the micro code with 112 instructions CE 454 Ahmed Ezzat

Part of Fig 4-17 Example: IJVM implementation CE 454 Ahmed Ezzat

An Example IJVM Implementation: Implementation of IJVM Using the Mic-1
112 microinstructions (microprogram) that runs on Mic-1 to interpret IJVM assembly instructions Additional Registers TOS: cache for memory location pointed to by the SP OPC: temporary scratch register Has main loop (main1:) to run the fetch-decode-execute cycles for IJVM instructions At the beginning of each IJVM instruction PC is incremented (pointing to the byte after the opcode). Current opcode is already fetched into MBR Fetch next byte into MBR Perform multiway branch to the address in MBR at the beginning of executing this instruction Microinstruction branches to the microcode for executing the IJVM instruction, and also begin fetching next byte: can be operand or next opcode Please go through the instructions in 4.3.2 CE 454 Ahmed Ezzat

END CE 454 Ahmed Ezzat

Register Transfer Language (RTL)
Can describe data path operations in RTL A useful shorthand for describing R to R ops and actually all others Same can be done for control logic Everything comes from and goes to register! Thus every operation can be described as register transfers Therefore through combinational logic CE 454 Ahmed Ezzat

RTL Notation (pseudo-notation)
Variables are (the contents of) registers Operations are assignment (of a new value) arithmetic and logical operations etc. Memory is a one dimensional array of a given length M[4] ( or R[4]) means location 4 of memory ( or register file) Example of operation and assignment R[4]  R[4] + R[6] (assignment stores into a register) Conditional operation Z  1 (Z has value 1) if R[4] = 0 We may use RTL notations to describe simultaneous operations (in time) MDR  Mem[MAR] ; PC  PC + 2 (these two operations are performed in parallel) CE 454 Ahmed Ezzat

RTL for a MOV instruction
MAR  Ri (or Ri + displacement) Set the next address to read in memory as the contents of the register Ri MDR  Mem[MAR] when Dready=1 When the signal Dready (Data Ready), store the contents of the memory address MAR into the register MDR Ri  MDR If we need the value in a specific register CE 454 Ahmed Ezzat

CE 454 Computer Architecture

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