1. Command & Data Handling
System
(C&DH)
David McGrogan
Space Sciences Laboratory
University of California, Berkeley

2. C&DH Agenda AGENDA Overview CPU Requirements CPU Hardware
Reset Behavior
Data Flow/Storage
Command Upload/Storage
Development Plan
Issues

3. Overview
SD Card
Main Processor
Peripherals

4. Requirements ID Title Description dsPIC33 Compliance CDH-01
Processing speed
>5 MIPS, >10KFLOPS
10 MIPS
CDH-02
RAM
>16kbytes (TBR)
30 KB SRAM
CDH-03
Program memory
> 32kbytes (TBR), reprogrammable
256 KB Flash RAM
CDH-04
Telemetry Recorder
> 200Mbytes FLASH
2GB SD card via SPI
CDH-05
Power
~100mW
for dev board, for processor
CDH-06
Cubesat compatible
Compatible with Cubesat Kit standards for form factor, sep switch interface, USB battery charging/debug interface, etc.
Processor card made by Cubesat Kit manufacturer
CDH-07
Transceiver Interface
Interfaces with Transceiver (data, power switching)
UART connection to Helium transceiver
CDH-08
High Rate Downlink
Interfaces with Sband Transmitter (downlink at 1Mbps)
SPI connection to Tx FPGA
CDH-09
STEIN Interface
Interfaces to STEIN via TBD interface to Instrument Interface Board (data stream, HVPS, bias, attenuator actuator)
SPI connection to instrument interface FPGA
CDH-10
MAGIC Interface
Interfaces to MAGIC via SPI or Instrument Interface Board (TBD)
CDH-11
Sun Sensor Interface
Interfaces to Sun Sensor via Instrument Interface Board
CDH-12
Torque Coil Interface
Interfaces to Torque Coil power swicthes via Instrument Interface Board (PWM in C&DH or FPGA TBD)
CDH-13
EPS Interface
Interfaces to EPS via I2C interface
I2C connection to EPS

5. CPU Microchip dsPIC33FJ256GP710 16-bit CPU 2 SPI channels (5 Mbps max)
2 UARTs (1 Mbps max)
2 I2C channels (0.4 Mbps max)
2 ECAN channels (can’t really use these)
10s of other pins (timers, ADCs, interrupts, GPIO)
30KB SRAM
Useful Features
Watchdog timer
Brown-out reset
Power-saving modes
Language Support
C compiler, simulator, other items are free
SALVO Real-Time Operating System (unused)
Actually do FP simulation, see if it gives useful info 5

6. Reset/Initialization
Hardware Reset
Power-On
Watchdog Reset
Ground Command
Reset Sequence
Initializes Local Data RAM to zero
Issues Initialization calls to each Module
Starts in Safe Mode (low power)
Begins Engineering Telemetry (1-sec)
Checksums available programs
Selects first program with good checksum
Waits 10 seconds
Runs selected program

7. Data Paths
PIC – Helium xcvr. (UART) PIC – EPS ( I2C ) PIC – SD card (SPI) PIC – FPGA (SPI) SD
CARD
FPGA – Tx (bitstream)
FPGA – STEIN (CDI)
FPGA – MAGIC (SPI)
Peak Data Flow
Tx : 1 Mbps continuous
SDCARD : 1-2 Mbps average (including RTOS)
STEIN: 16 bits/event, 80KHz events = 1.28Mbps
MAGIC: 19 bits x 20 Hz x 3 axes = Mbps
Helium 100: Mbps

8. Data Movement Pipelined data flow Standard buffering
For high-volume data flow (STEIN and Tx)
Begin STEIN data import to DMA (512B DMA block)
Immediately begin SD card data export from DMA
Data transfer completes at maximum speed
Requires a block of DMA (512B of 2KB available on chip)
Standard buffering
For smaller volumes of data (MAGIC)
Read data explicitly without DMA, store in RAM
Write to SD card when buffer sufficiently filled

9. Holds 4.5x the amount downloadable in one pass
Solid State Storage
2 GB SD card
Holds 4.5x the amount downloadable in one pass
Blocks from 1 to 512 bytes possible
Using 512 byte blocks to minimize overhead, increase expandability (SDHC only allows 512B)
Multiple independent circular buffers for engineering, MAGIC, and STEIN data; STEIN buffer is at least half the space (>=500M 16-bit events)
Eng.
MAGIC
STEIN

10. Command uploading and storage
1200 Bps link through Helium
4-byte UART FIFO would need handling at 300 Hz
75 bytes of DMA needed for 16 Hz handling
Uploaded commands are moved to non-DMA circular buffer and handled in order
Commands execute ASAP or at a given future time (expressed in relative time)

11. Development plan
Near future:
Write SD card access code
Characterize SD card read/write speed and power req.s
Establish communication protocol with FPGA

12. Issues
Warm-restart possibility – preserve local time and data across undesired resets, execute commands on time (most dsPIC registers are unaffected by a reset)
240 mW MB draw is over ~100 mW requirement; virtually all load due to non-processor parts (e.g. line buffers), potentially different for flight board vs. dev board
Power-saving dsPIC modes available, may be irrelevant
Memory allocations (especially 2K DMA area)
Uploading multiple programs – machine code requires some effort to move in program memory (e.g. direct jumps, interrupt pointers)

14. Flight Software Veer Bawa UCB/SSL Space Sciences Laboratory
University of California, Berkeley

15. Flight Software Agenda
Overview
Requirements
Design
Foreground Tasks
Background Timing
Modes & Enables
Actuators
Development Plan
Issues

16. Flight Software is broken into 13 major modules:
Overview
Flight Software is broken into 13 major modules:
Executive (EXEC) – runs long-term tasks
Background (BKG) – runs routine tasks regularly
Housekeeping (HSK) – samples engineering values
Load (LD) – loads/dumps memory, scans SRAM for errors
Command (CMD) – decodes/distributes commands
Telemetry (TM) – multiplex packets and control transmitter
I/O (IO) – interface to board hardware
Utilities (UTIL) – common utilities for all modules
Power (PWR) – controls power supply to components
Attitude Control System (ACS) – runs ACS calculations
Solid State Manager (SSR) – interfaces with SD Card
STEIN Control – STEIN interface
MAG Control – MAG interface
Perhaps add MAG and STEIN as their own modules instead of I/O; I/O is in Phase 1, but shouldn't these two be in Phase II?
I'm thinking of moving this into the Development page, and putting a description of the modules here That doesn't seem quite right, but(I can't think of any other overview
THIS TABLE IS OBSOLETE (DIFFERENT PROJECT IN FACT)

17. Level 2 Requirements

18. Level 2 Requirements

19. Level 2 Requirements

20. Design FSW MAJOR MODULES I II IV III
Helium
Cmds
Analogs I II IV
III
Simulink
PWR.A
ACS.A
Sun
Sensors
Torque
Coils
STEIN
Atten
MAG
Elect
MAG.A
STEIN.A
SPI
S-Band Tx
TM.A
SDCARD
FPGA
POWER
Switches
Timers
BKG.A
EXEC.A
SSR.A
LD.A
CMD.A
SRAM &
EEPROM
HSK.A
COMM
FSW MAJOR MODULES
MAG and STEIN are not listed as modules in the Phase I/II/III table; do they need to be added there or replaced here with I/O

21. Tasks Two kinds of tasks Foreground tasks (called by EXEC module)
Run asynchronously in available time
No hard limit on execution time
Configurable by ground commands
ACS, SRAM scan, memory peek/poke…
Background tasks (called by BKG module)
Run at specific times
Must complete before next interrupt (~9700 instructions)
Performs tasks that must occur on time
Data flow management, MAG sampling, housekeeping ADC sampling… 21

22. Foreground Task Operation
Foreground tasks
Round-robin loop of standard tasks (e.g. attitude determination)
Will be frequently interrupted by background tasks, so should not rely on shared peripherals maintaining their state (may put off-chip I/O in a specialized background task)
Additional tasks can be added by commands from ground; stored in SRAM
Uploaded tasks have scheduling field – “run at time T”
Many commands can be uploaded as a burst 22

23. Background Timing Timing Interrupt 1024 Hz interrupt schedule
BKG module distributes CPU time per table
Full table repeated at 16 Hz
Table independent of mode
Each ISR checks the enable bits before running
A few slots are left empty, to be used later as needed

24. Modes & Enables FSW Modes
Safe – Minimal Power Configuration, Resets to Safe, all optional bits off
ACS – only Flash, Torquer, and LV MAG on, Used to control attitude
Science - SDCARD Allowed, STEIN, S-Band Allowed, Actuators Disabled
Engineering – Everything enabled
Enable Mask Table Used to Maintain Power Balance

25. Actuators Actuations MAG Boom
Released by .25 to .50 second pulse to unit
Actuator Enable must be commanded on
STEIN Attenuator
Moving In / Out Controlled by FSW using STEIN count rates
Damage to Attenuator if commanded to reverse direction too soon
FSW automatic lockout for 120 (commandable) seconds after actuation
UHF Antenna
- Must be automatically deployed initially, using a countdown timer
- Must ensure that reset during countdown does not affect time of
deployment adversely (i.e. too early or not at all) 25

26. Development Plans Development Pumpkin Development Board + Laptop PC
MPLAB30 “C” Compiler, Simulator, Debuggers
Subversion (SVN) for storing source code and documents
Corresponding TRAC wiki to track changes and issues (e.g. bugs)
GSE Laptop running GSEOS
FSW Developed in phases:
CPU/Mother Board Only
CPU/Mother Board + [EPS, Batt, UHF, IIB]
CPU/Mother Board + [EPS, Batt, UHF, IIB] + [HVPS,STEIN, MAG]
Verification Matrix Provides Status of Requirements
Comprehensive Performance Test on Development Board
Load into Flight System
Joins CINEMA Test Flow and Quality reporting

27. Verification FSW Verification
CINEMA_FSW_002_Requirements.xls tracks requirement flows
Reqmt
Description
Verification
Parent
Rationale
FSW.BKG-1
BKG shall provide timing for the FSW.
Test
FSW-18
Use processor timers to maintain an on-board clock used to time-tag packets and frames. Clock shall be adjustable by ground command, and return to zero on reset.
FSW.BKG-2
BKG shall update the Watchdog Timer at 1 Hz
FSW.BKG-3
BKG shall distribute the interrupt timing to other modules
Development status, test overview and procedure name
Note: Sample Only 27

28. Issues
Required resources for ACS unknown; is a background task needed?
SD Card overhead unknown

29. Direct Memory Access (DMA)
2KB
STEIN
COMM

30. SPI

31. FSW Requirements

32. FSW Requirements