1. Firmware Structure Alireza Kokabi Mohsen Khakzad Friday 9 October 2015
School of Particles and Accelerators, Institute for Research in Fundamental Sciences (IPM)
Friday 9 October 2015

2. Readout Scheme FPGA POH POH POH POH Trigger HPTDC HPTDC HPTDC HPTDC
CCU25
POH
HPTDC
DAC
JTAG
CCU25
POH
HPTDC
JTAG
FPGA
CCU25
POH
HPTDC
JTAG
CCU25
POH
HPTDC
JTAG
Trigger
09-Oct-2015

3. Firmware Tasks Generating Token Signals for HPTDC
Reading data from HPTDC
Decoupling input and output data streams using implemented FIFO
Taking configuration parameters from DAQ system
Sending current acquisition settings to DAQ system
Digital Clock Propagation
Setting Threshold Voltage through DAC imbedded in the NINO board
Bringing readout data into designed format
Sending formatted data to DAQ system
Configuration of the HPTDC through JTAG
Generating Orbit Number
09-Oct-2015

4. CCU25 CCU25 4 Bidirectional 8-bit parallel port 16 CMOS I2C buses
Strobe In A
Strobe Out A
Port A
CCU25
TCK
TMS
TDI
Strobe In B
Strobe Out B
Port B
TDO
Strobe In C
Strobe Out C
Port C
I2C
Strobe In D
Strobe Out D
Port D
4 Bidirectional 8-bit parallel port
16 CMOS I2C buses
1 Master JTAG port
Max clock frequency: 60MHz
09-Oct-2015

5. Control Ring
09-Oct-2015

6. POH POH 4 LVDS Channels Max frequency: 400MHz IN1+ IN1- IN2+ IN2- IN3+
09-Oct-2015

7. HPTDC HPTDC 32-bit parallel interface Max Parallel Data Rate: 40MHz
TCK
HPTDC
TMS
TDI
TDO
TRST
Data
Serial Out
Data Ready
Strobe Out
Token Out
Token In
32-bit parallel interface
Max Parallel Data Rate: 40MHz
JTAG Programmable
09-Oct-2015

8. Firmware Structure
We have 4 POH channels, 4 CCU25 parallel ports, 4 HPTDCs, 1 DAC, 4 Separated JTAG ports
Firmware deals with each HPTDC separately
We have four (almost) similar chains, each chain for readout of one HPTDC
Advantages:
Faster chains per HPTDC
Problem with one chain does not affect on the other
09-Oct-2015

9. Parallel Readout Chains
HPTDC
DAC
JTAG
CCU25
POH
HPTDC
JTAG
CCU25
POH
HPTDC
JTAG
CCU25
POH
HPTDC
JTAG
CCU25
POH
09-Oct-2015

10. Readout Chain Readout Chain Trigger POH HPTDC 09-Oct-2015 CCU25 DAC
JTAG
Readout Chain
Trigger
CCU25
POH
09-Oct-2015

11. Readout Chain Readout Chain
Acquisition Chain (for taking data from HPTDC and transmit it through POH)
Control Chain (for setting configuration parameters)
09-Oct-2015

12. Control Chain Control Decoder
Readout Controller
Control Decoder receives instructions from CCU25
Based on the type of instruction:
Request sending data from readout controller
Set threshold voltage
Configure HPTDC
Verify HPTDC
Request Transmitting Data
Configuring HPTDC
Getting Configuration Data
Control Decoder
JTAG Controller
CCU25 Interface
Verifying HPTDC
Sending Status Data
DAC SPI
Setting Vth
09-Oct-2015

13. Acquisition Chain
Serial Interface
Transmitting Data through POH
Bringing Data into Format
Saving Data in FIFO
Dual Bus FIFO
Parallel Interface
Adder
Orbit Number
Request Transmitting Data
Readout Controller requests Adder to transmit data from
After receiving this request, Adder reads N values from the FIFO, Bunch Number from Orbit Counter, and Run Number From Control Decoder and concat them together according to the Data Format
Readout Controller
Orbit Counter
Run Number
Trigger
09-Oct-2015

14. Clock Scheme Four main clock sources: 40MHz 80MHz 320MHz Max 600MHz
Core Frequency
HPTDC Data Interface
POH Serial Interface
HPTDC JTAG Interface
DAC SPI Interface
CCU25 Parallel Port
Max
600MHz
40MHz
400MHz
10MHz
60MHz
Used
320MHz
100KHz
09-Oct-2015

15. FIFO Characteristics
Four similar FIFOs are implemented in the firmware (one per HPTDC)
Each FIFO size is 5K x 23bit (5K edge measurements)
If this FIFO size is not enough, then FIFO should be implemented on external RAM
Clock for this FIFOs are similar to the core clock (320MHz)
Data from the HPTDC parallel port is directly saved in this FIFO
09-Oct-2015

16. IOs Number of IOs defined in this firmware Number of IOs Connection 53
HPTDC 8
DAC 4
Clock
POH 52
USB 40
CCU25 6
Others
09-Oct-2015

17. JTAG Controller Four separate JTAG master 5-wire LVTTL signals
HPTDCs are not chained
10MHz clock frequency
09-Oct-2015

18. Threshold Voltage Setting
One 4-wire 16-bit SPI interface is implemented (CMOS)
DAC has 8 channels, 4 channels are used (TH1+, TH1-, TH2+, TH2-)
Around 1v bias voltage applied to channels (Bias voltage is not calibrated)
The difference between TH+ and TH- is calibrated
09-Oct-2015

19. Firmware Flashing Options
Firmware can be flashed through dedicated JTAG port
CCU25
CMOS to LVTTL
TCK
TCK
TMS
TMS
TDI
TDI
FPGA
TDO
TDO
JTAG Conn.
CCU25 Master JTAG works at 2.5v (CMOS Standard)
TCK
TMS
TDI
FPGA JTAG Port is at 3.3V (LVTTL Standard)
It can also be at 2.5v (CMOS Standard)
TDO
09-Oct-2015