1. Lecture 15 PicoBlaze Overview
ECE 448 – FPGA and ASIC Design with VHDL

2. ECE 448 – FPGA and ASIC Design with VHDL
Required reading
P. Chu, FPGA Prototyping by VHDL Examples
Chapter 14, PicoBlaze Overview
Recommended reading
K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6)
ECE 448 – FPGA and ASIC Design with VHDL

3. FPGA with Soft Processor Core
PicoBlaze
Source: The Zynq Book

4. Structure of a Typical Digital System
Data Inputs
Control Inputs
Control
Signals
Datapath
(Execution
Unit)
Controller
(Control
Unit)
Status
Signals
Data Outputs
Control Outputs

5. ECE 448 – FPGA and ASIC Design with VHDL
Block diagram of a Single-Purpose Processor (FSMD – Finite State Machine with Datapath)
ctrl
ECE 448 – FPGA and ASIC Design with VHDL

6. Block diagram of a General-Purpose Processor (Microcontroller)
ECE 448 – FPGA and ASIC Design with VHDL

7. ECE 448 – FPGA and ASIC Design with VHDL
PicoBlaze-3
ECE 448 – FPGA and ASIC Design with VHDL

8. PicoBlaze-3 Overview

9. PicoBlaze-6 Overview

10. PicoBlaze-6 Overview

11. Size of PicoBlaze-6 in Spartan 6
Make an educated guess
Resource Utilization in CLB Slices ?
Number of PicoBlaze-6 cores fitting inside of the Spartan-6
FPGA (XC6SLX16) used on the Nexys3 FPGA board

12. Size of PicoBlaze-6 in Spartan 6
Resource Utilization in CLB Slices
26 CLB Slices
1.1% of Spartan-6 used in Nexys3
Number of PicoBlaze-6 cores fitting inside of the Spartan-6
FPGA (XC6SLX16) used in the Nexys3 FPGA board
87 PicoBlaze cores

13. Speed of PicoBlaze-6 in Spartan 6
Make an educated guess
Maximum Clock Frequency ?
Maximum number of instructions per second

14. Speed of PicoBlaze-6 in Spartan 6
Maximum Clock Frequency
105 MHz
Maximum number of instructions per second
52.5 millions of instructions per second (MIPS)

15. Register File of PicoBlaze-31 7
Address
16 Registers
8-bit F s0 s1 s2 s3 s4 s5 s6 s7
Register File of PicoBlaze-3 2 3 4 5 6 7 sF

16. Register File of PicoBlaze-6
Instructions
REGBANK A
REGBANK B
used to switch between banks
Only one set of flags
Z, C, I
Very useful for
interrupt service routines

17. overflow, underflow, or various conditions
Definition of Flags
Flags are set or reset after ALU operations
Zero flag - Z
zero condition
Z = if result = otherwise
Carry flag - C
overflow, underflow, or various conditions
Example*
C = if result > (for addition) or
result < 0 (for subtraction)
otherwise
*Applies only to addition or subtraction related instructions, refer to the following slides otherwise

18. Interface of PicoBlaze-3
KCPSM = constant (K) coded programmable state machine
ECE 448 – FPGA and ASIC Design with VHDL

19. Interface of PicoBlaze-3
Name
Direction
Size
Function
clk
input 1
System clock signal.
reset
Reset signal.
address
output 10
Address of the instruction memory.
Specifies address of the instruction to be retrieved.
instruction 18
Fetched instruction.
port_id 8
Address of the input or output port.
in_port
Input data from I/O peripherals.
read_strobe
Strobe associated with the input operation.
out_port
Output data to I/O peripherals.
write_strobe
Strobe associated with the output operation.
interrupt
Interrupt request from I/O peripherals.
interrupt_ack
Interrupt acknowledgment to I/O peripherals
ECE 448 – FPGA and ASIC Design with VHDL

20. Interface of PicoBlaze-6
Name
Direction
Size
Function
clk
input 1
System clock signal.
reset
Reset signal.
address
output 12
Address of the instruction memory.
Specifies address of the instruction to be retrieved.
instruction 18
Fetched instruction.
port_id 8
Address of the input or output port.
in_port
Input data from I/O peripherals.
read_strobe
Strobe associated with the input operation.
out_port
Output data to I/O peripherals.
write_strobe
Strobe associated with the output operation.
interrupt
Interrupt request from I/O peripherals.
interrupt_ack
Interrupt acknowledgment to I/O peripherals
ECE 448 – FPGA and ASIC Design with VHDL

21. Interface of PicoBlaze-6
ECE 448 – FPGA and ASIC Design with VHDL

22. Additional Ports of PicoBlaze-6
Name
Direction
Size
Function
bram_enable
output 1
Read enable for the program memory. This signal should be connected to the enable input of the program memory and is used to reduce the power consumption associated with the BRAM(s).
k_write_strobe
This output will pulse High for one clock cycle when KCPSM6 executes an ‘OUTPUTK’ instruction and the peripheral logic should capture the data provided on ‘out_port’ into the intended destination defined by the value of ‘port_id[3:0]’. Note that only the lower 4-bits of ‘port_id’ are used during ‘OUTPUTK’.
sleep
input
Active High sleep control. When driven High KCPSM6 will complete the current instruction and then enter a sleep mode in which all activity stops. Whilst in the sleep mode all strobes are inactive and the ‘bram_enable’ is Low to disable the program memory resulting in minimum power consumption. All inputs except ‘reset’ are ignored. When ‘sleep’ is returned Low, KCPSM6 resumes execution from the point that it stopped.
ECE 448 – FPGA and ASIC Design with VHDL

23. Generics of PicoBlaze-6
Name
Default
Range
Function
hwbuild
X”00”
X”00”..X”FF”
can be used to define any 8-bit value in the range ‘00’ to ‘FF’. It is then possible to load any KCPSM6 register with this value using the ‘HWBUILD sX’ instruction
interrupt vector
“X3FF”
X”00”..X”FFF”
When an interrupt occurs (and interrupts are enabled) then KCPSM6 inserts and executes a special form of CALL instruction to a fixed address known as the interrupt vector. By default
this address is ‘3FF’ (the last location of a 1K program memory).
scratch_pad_ memory_size 64
64, 128, 256
Size of the scratch pad memory. Increasing the default size to 128 (256) bytes, increases the resource utilization
by 2 slices (6 slices).
ECE 448 – FPGA and ASIC Design with VHDL

24. PicoBlaze-6 Instantiation
ECE 448 – FPGA and ASIC Design with VHDL

25. ECE 448 – FPGA and ASIC Design with VHDL
Development
Flow of a
System
with PicoBlaze
ECE 448 – FPGA and ASIC Design with VHDL

26. PicoBlaze-3 Programming Model
ECE 448 – FPGA and ASIC Design with VHDL

27. PicoBlaze-6 Programming Model
Bank B
Bank A
FFC
FFD
FFE
FFF
ECE 448 – FPGA and ASIC Design with VHDL

28. Syntax and Terminology
Syntax Example Definition sX KK
PORT(KK)
PORT((sX))
RAM(KK) s7 ab
PORT(2)
PORT((sa))
RAM(4)
Value at register 7
Value ab (in hex)
Input value from port 2
Input value from port specified by register a
Value from RAM location 4

29. Addressing modes Immediate mode SUB s7, 07 s7 – 07  s7 ADDCY s2, 08
s C  s2
Immediate mode
SUB s7, 07
ADDCY s2, 08
Direct mode
ADD sa, sf
INPUT s5, 2a
sa + sf  sa
PORT(2a)  s5
Indirect mode
STORE s3, (sa)
INPUT s9, (s2)
s3  RAM((sa))
PORT((s2))  s9

30. PicoBlaze ALU Instruction Set Summary (1)

31. PicoBlaze ALU Instruction Set Summary (2)

32. PicoBlaze ALU Instruction Set Summary (3)