Phase 2 Muon Electronics

Phase 2 Muon Electronics
C. F. Bedoya General Muon Meeting February 25th, 2013

CMS TPSWG Phase 2 > LS3 This is mainly just a heads up about what is being discussed in CMS. Interim report from the TPSWG (Trigger Performance Strategy Working Group): TPSWG charges: to establish a plan for CMS triggering options during Phase 2. Even if you think you will be retired by 2022, think of what you want to do until then... (R&D takes years) C. F. Bedoya February 25th, 2013 2

AND maybe not so much Pixel trigger? (or 25 us...)

Other intermediate points that alleviate the cost and time of needed intervention should be given (if they exist) We are being asked this

Present knowledge ECAL: limit is 150 kHz & 6.4 us (maybe 300 kHz?). > => 26 months shutdown, 10 MCHF Tracker: very much in favor of increasing latency (20 us) if rate increased, happy with 500 kHz, 1 MHz not impossible HCAL: changes limited to USC, does not seem a major constraint at present. RPC: Probably changed by LS2. All in USC. Any increase L1A param => keuros (84 RMBs, 3 FEDs) CSC: Good at increased L1A rate, bad at increased latency >300 kHz & 6.4 us => 4 months & 12 MCHF. 500 kHz possible at all? which implications Is it worth changing just a fraction of the CFEBs? Do you expect any longevity issue that would make worth a re-desing independently from this? 1 MHz & 20 us => 4 months & 12 MCHF ? Is that true? DT: The other way around... latency OK, rate overkilling 300 kHz & 20 us => OK (to check) 500 kHz & 20 us => YB-/+2 MB1 and MB4s? 6 months?, cost? 1 MCHF? Evaluate Possibility open that we need to replace Minicrates either way.. maybe not all in one goal, but the R&D should be launched soon 1 MHz & 20 us => 1-2 years & 5 MCHF ? Probably more... Evaluate C. F. Bedoya February 25th, 2013 5

CSC constraints L1A 6 us and 300 kHZ => OK without changes Safe
Promising methods to reduce the CFEB pre-trigger rate by a factor between 3-6 (4 layers, anode trigger, tight TMB patterns...) obtain low payload, but increase latency.... These steps do not appear sufficient to allow high efficiency CSC readout and trigger with 1 MHz L1A rate and 20 sec latency, and for any other scenario, a variety of tests would are needed beforehand to guarantee the safe operation. Safe 6us-500 kHz ok??? at which cost? Increase in latency is worst than increase in rate (20 us, 25 us... does not matter, full replacement) C. F. Bedoya February 19th, 2013 6 Thanks to S. Durkin

When can replacement happen?
We have a big constraint and it is the large time needed to perform any intervention in our detector. Very unlikely that we get access time for all of our needs: LS1.5?: new pixel LS2: GEMs?, GRPC? HCAL? LS3: New Tracker, New ECAL FE Whatever we invent, will likely need to coexist with present electronics but at the same time, the architecture could be completely different if 20 us latency is granted... C. F. Bedoya February 25th, 2013 7

C. F. Bedoya February 25th, 2013

Some comments Imo simulations of the impact of inefficiency in the detector in the physics analysis do not exist. A muon joint effort would make sense on this. Probably even less if one refers to simulation of the electronics (readout), and this is one of the main points we are asked.... In reality probably the power supplies and the cooling are the point of major concern for the long reliability of the system... (though not much design we can do on that...) But for custom electronics we need time for brainstorming and for putting together the manpower and the budget (different timescales for different institutes, etc), so discussions on what can be done should take place now. Different L1A parameters may imply some challenge in the electronics.. it may be more interesting that to rebuilding the same wheel... Or maybe what we want to think is in replacing subdetectors technology.. but I doubt that. C. F. Bedoya February 25th, 2013 9

BACK-UP C. F. Bedoya February 25th, 2013 10

Imo, we need to seriously start thinking about long term scenarios:
-Very, very unlikely we can change all the Minicrates in the same shutdown -Changing full Minicrate can be faster than only a fraction of its boards (and safer) -It took 7 years to build minicrates, it means, start in -Order of magnitude budget should be established asap -Ideally we want a change of concept (bringing out digitized data in continuous mode...) is there any way to make it coexisting with present system? Plan for other parts (FEBs, HVB, chambers... ) I guess it is mainly crossing fingers... More details on monday... C. F. Bedoya February 21st

DT constraints Minicrate ROB
* Latency increase has a moderate impact (buffers quite large) * L1A rate increase is the killing part (opposite to CSCs ) due to output link speed Minicrate Other layer of electronics on top Plus plenty of cables... ROB C. F. Bedoya February 25th, 2013 12

DT muon rate estimations
Phi rates YB-/+2 MB1s at 1035 : 350 kHz “muon” rate (per chamber) 114 kHz “muon” rate per ROB 29 kHz “muon” rate per TDC This are chamber rates (DTTF input counters) - Occupancies are quite inhomogeneus. - Uncertainties are large. - Small differences have a large impact From I. Redondo C. F. Bedoya February 19th, 2013 13

DT Updates 100 kHz and 6 us latency OK without changes
300 kHz and 20 us latency Should be OK but needs further testing 500 kHz and 20 us => It could work replacing a fraction of the detector (testing needed): YB-/+2 MB1s: 6 months shutdown fully DT devoted, 1 MCHF? Shielding in MB4s 1 MHz and 20 us => all ROBs to be replaced: 1-2 years shutdown fully DT devoted, 5 MCHF? 25 us => all ROBs to be replaced: 1-2 years shutdown, 5 MCHF? Latest discussions in DT point to a need of replacing all the Minicrates at some point in Phase 2 (doses need further radiation tests) The timescale is still not clear, but: 7 years for R&D 1-2 years replacement The design changes significantly if not all the Minicrates can be replaced simultaneously. At that point, latency and rate become irrelevant. C. F. Bedoya February 19th, 2013 14

CSC constraints L1A 6 us and 300 kHZ => OK without changes Safe
Promising methods to reduce the CFEB pre-trigger rate by a factor between 3-6 (4 layers, anode trigger, tight TMB patterns...) obtain low payload, but increase latency.... These steps do not appear sufficient to allow high efficiency CSC readout and trigger with 1 MHz L1A rate and 20 sec latency, and for any other scenario, a variety of tests would are needed beforehand to guarantee the safe operation. Safe Increase in latency is worst than increase in rate (20 us, 25 us... does not matter, full replacement) C. F. Bedoya February 19th, 2013 15 Thanks to S. Durkin

CSC constraints Any option beyond 300 kHz and 6 us latency imply the replacement of a fraction (chambers with higher occupancy) or of all of the CSC CFEBs. These scenarios have similar and important consequences: -Access to the wheels is estimated roughly in 4 months period during a shutdown with some important assumptions: no change in the CFEB power and LVDB and ALCT boards not replaced. -New DCFEB board would need to be designed and produced (2600 for the full detector). Present one used for ME1/1 will not be usable because it uses a factor 3 more power than CFEBs and contain Amp (Buckeye) and Comparator ASICs which are no more available. -CERN microelectronics group would be requested to design new version of this ASICs. - US physicists/engineers on DCFEB project presently 58 & 60 years old. New technical experts needed. -oDMBs will also need to be designed and built by the CSC group (500 oDMBs for the full detector) -New fibers will need to be routed from the chambers to the peripheral crates Cost estimated would be roughly 12 MCHF for the full replacement. C. F. Bedoya February 19th, 2013 16 Thanks to S. Durkin & J. Hauser

CSC constraints We could also envisage a scenario in which only the higher occupancy chambers are replaced (ME2/1, ME3/1, ME4/1 36 chambers each) which could cost approximately 2.5 MCHF. With this it is likely that we could stand 1 MHz L1A rate and 8 us latency (this needs to be studied in more detail), but to achieve 20 us latency everywhere, all chambers need replacement. C. F. Bedoya February 19th, 2013 17 Thanks to S. Durkin & J. Hauser

Around LS2 most probably current electronics of the RPC PAC system will be replaced by the new Muon Track Finder, which will have to assure readout of the RPC data. What if not: No intermediate hardware modification are possible to improve the RPC DAQ performance in the current RPC PAC trigger electronic system. Needed hardware modification: new readout RMB mezzanines (RMB) on the Trigger Boards, new DCC (FED), faster link RMB-DCC Some improvements are potentially possible with the modification of the firmware and configuration: Increasing of the latency: the buffer in the RMB (implemented in the FPGA memory) can be increased scarifying the diagnostics implemented in the chip: spy readout and input data counters. To say how much – the firmware modification should be implemented and tested. Increasing of the L1A accept rate: one have to reduce the amount of data send from the RMB to the DCC. It is possible by: Reducing the number of the BXes recorded for each event The LB-TB optical links are split, i.e. each go to 2 or 4 TBs, and now are readout from each TB. The RMBs can be configured such that each link is readout only once. To test these modifications, just the configuration needs to be updated. Increase in the RPC detector occupancy with the higher luminosity needs to be included, so in practice it might be that we will not be able to gain much. TPSG 19 February 2013 Karol Buńkowski, CERN, UW,

To the Global Muon Trigger
RPC PAC muon trigger Detector Counting room Control & diagnostic LVDS cables Link Board Synchronization Unit & LMUX Trigger Board Ghost Buster & Sorter SYNCH. & LDMUX PAC GB & Sorter Optic Links GHz 1104 fibers PAC 1232 Link Boards in 96 Boxes, Steered by Control Boards To the Global Muon Trigger FEB PAC FEB Data Concentrator Card Co to Counting room RMB 84 Trigger Boards in 12 Trigger Crates Data 320 MHz To Data Acquisition Resistive Plate Chambers Up to 6 layers of detectors. 480 chambers in barrel, 504 in endcaps * Numbers of elements for the staged version of the system CMS GEM LS1 DAQ, 21 January 2013 Karol Buńkowski, UW

RPC constraints * If L1A latency and/or trigger rate increase (>200 kHz), one would need to exchange: - RMB (Readout Mezzanine Board) (84), Optical Links (84), DCC board (3) * Cost exercise: keuros, everything in USC * Present PAC trigger will likely be replaced before LS2 with an integrated muon trigger system. So in principle, no limitation should be foreseen in that case to run at 1 MHz and us. (Worst case scenario, previous numbers) February 19th, 2013 21

BACK-UP

RPC constraints RMB Trigger Board x84 DCC x3
The current RPC DAQ system: RMBs (84): readout buffers, pack Link Boards incoming data and send them to the DCCs via the optical Mbit/s DCC – RPC FEDs (3): S-link to the DAQ. These are ECAL boards with our custom firmware. Higher L1A rates or higher latency will require: - RMB: bigger and faster FPGA needed - Optical link bigger bandwidth would have to be used, - DCCs: would have to be replaced with new boards (CMS generic?). Trigger Board x84 DCC But… will RPC trigger electronics remain unchanged until LS3?? x3 C. F. Bedoya June 29th, 2012 23 Thanks to K. Bunkowski

RPC constraints 3. Data volumes after LS3
* No estimations done yet, but no big surprises expected * About ~50% of the data transmitted to the DAQ are format frames (size constant w.r.t. luminosity) From A. Holzner Electronics Week * RPC event size is very low comparing to the other subsystems (100 bytes) * Does not seem to depend on pile up C. F. Bedoya June 29th, 2012 24 Thanks to K. Bunkowski

DT constraints 1. Increase L1A latency (6, 10 or 20 µsec?) IN PRINCIPLE OK Parts affected: ROBs (4 CERN´s HPTDC/ROB): * HPTDCs can accept L1A latencies up to 25 µsec. * Occupancies low in DT, shouldn´t cause buffers filling up. * But… needs to be tested. The rest of the affected parts (DTTF, TSC (to a minor extent)) are supposed to be redesigned in Phase 1. NOTE: If it is not ok, replacing the ROBs is a VERY MAJOR EFFORT (it is inside the detector) C. F. Bedoya June 29th, 2012 25

DT constraints 2. Increase L1A trigger rate (200 kHz or 500 kHz or 1 MHz?) 1st bottleneck: ROS processing time * It is designed to run at L1A 100 kHz @ 1034 cm-2 s-1 ROS processing time depends on hits distribution in the detector Max equiv L1A freq (kHz) We plan to redesign the ROS <2017 As it will be in USC after LS1, we could easily accept higher rates BUT if possible redesign only ONCE (would like to know the LS3 L1A latency and rate requirements) C. F. Bedoya June 29th, 2012 26

DT constraints 2. Increase trigger rate (200 kHz or 500 kHz or 1 MHz?)
2nd bottleneck : DDU processing time * DDU limit is 250 Mbytes/s * Present event sizes are < 1 kbyte (max 250 kHz L1A?) but event sizes will increase (see next slide) 3rd bottleneck : ROB output link bandwidth * TDCs could be still ok at 1 MHz L1A rate but… * output link maximum bandwidth for a L1A rate of 800 kHz (optimistically)… to be tested C. F. Bedoya June 29th, 2012 27

DT constraints 3. Data volumes after LS3
We are also interested to know what data volume we might expect from your detector after LS3. Assuming the readout remains as present (i.e. ROBs unchanged), this are the projections: Preliminary calculations worst case FED (external wheels): 1034 => 1 kbyte/FED (100 1035 => 6 kbytes/FED (600 5 FEDs in DT => 1 FED/wheel DDU limit is 250 Mbytes/s (limit at cm-2s-1 ?) However: * We can easily double the number of FEDs (running like that in 2010) * We can still reduce significantly the payload (trigger debugging data) * ROS board will be redesigned, FED concept may change (absorb FEDs in ROS design?) C. F. Bedoya June 29th, 2012 28

DT constraints Full readout of your subsystem at the crossing frequency of 40 MHz? * If no event matching is performed in the TDCs maybe we can readout all hits as they arrive * Drift time information referred to the BC0? * Needs more deep thinking and testing - Would like to test if in present ROBs this can be done (without rebuilding them). - Tricky but maybe not impossible - Also, would it be needed? (maybe higher L1A rate is acceptable for ROBs) - If ROBs are to be rebuilt for aging, then it is an interesting option C. F. Bedoya June 29th, 2012 29

CSC constraints IF CFEB SOLVED, SECOND BOTTLENECK
CFEB: MAIN BOTTLENECK 400 ns pulses Digitize at 25 ns Full readout of all CSC strips at 40 MHz is not an option ~5.7 Mbytes/Bx Data volume reduction is achieved by filtering read out info by means of local trigger primitives (LCT) in combination with L1A. (Local Charge Track Triggers (ALCT&CLCT) & L1A required to readout) C. F. Bedoya June 29th, 2012 30 Thanks to S. Durkin

CSC constraints MAIN BOTTLENECK CFEB
Analog storage in SCA (Switch Capacitor Array): - 96 strips/CFEB - 96 capacitors/strip - 400 ns strip pulse - Stored until LCT is received - Digitization and readout happens if LCT+L1A coincidence The higher the L1A latency the worst (longer time until digitization can start) The rate and latency limitations come from the SCA overuse probability µsec L1A latency + CLCT rate (poisson statistics) - 26 µsec digitization + L1A rate (queue statistics) The higher the L1A rate the worst (more samples to digitize) Higher detector occupancy (HL-LHC) only emphasizes the problem (higher input rates, higher CLCT rates) (Presently CLCT rate poorly known for LH-LHC ) C. F. Bedoya June 29th, 2012 31 Thanks to S. Durkin

CSC constraints At 6 µs L1A latency, one each 10000 samples lost
Situation gets worst as the L1A rate increases C. F. Bedoya June 29th, 2012 32 Thanks to S. Durkin

CSC constraints DCFEB (Digital CFEB ME1/1 Upgrade 2013)
Replace Conventional ADC and SCA storage with Flash ADC and Digital Storage - 96 strips/CFEB - Flash ADCs digitize all strips at 40 MHz - FPGA memory used as digital pipeline - Triggered events fiber readout at 2.5 Gbits/s * L1A latency irrelevant (huge FPGA block RAMs): 6, 10, 20 µsec (all fine) * Buffer Overflow depends weakly on L1A rate 1e-05 C. F. Bedoya June 29th, 2012 33 Thanks to S. Durkin

CSC constraints Why not build DCFEBs for all CSC?
* Assume Upgrade all Chambers to DCFEBs => 12 million dollars * Manpower: US physicists/engineers on DCFEB project presently 58 & 60 years old New technical experts needed. * We would need to produce more ASICs - Buckeye ASIC 16 channel amplifier shaper - Comparator ASIC 16 channel trigger primitives * At the time of LH-LHC upgrades CSC electronics will be 20 years old! so… If this were done, next bottleneck would be the SLINK readout, ideally one could go to 800 kHz L1A rate, though DDU has not been tested in this conditions, so no straight answer can be given at this point. 15 DCFEBs / DDU board. 4 VME crates with 9 DDU boards and 1 Data Concentrator board (DCC) in each crate. 2 SLINK/DCC, meaning 8 SLINKs in total. We are presently at the SLINK bandwidth limit. Our boards are configurable so that we have various ways of adding SLINKs. We can even get rid of the DCC boards and put an SLINK on each DDU giving us a total of 36 SLINKs. C. F. Bedoya June 29th, 2012 34 Thanks to S. Durkin

CSC constraints 3. Data volumes after LS3
We are also interested to know what data volume we might expect from your detector after LS3. Present data volume per chamber is ~2 kbytes. We presently average 3.3 chambers/L1A. Not clear how will scale. From A. Holzner Electronics Week Presently 6.6 kbytes in CSC, vertexes?? (needs further studies) C. F. Bedoya June 29th, 2012 35

DT constraints DT: How to get around the DDU limit for the readout speed and at what effort/cost? DDU limit can be a problem ONLY if L1A rate is increased (no effect with the latency) At present, we can probably sustain 500 kHz by doubling number of FEDs and reducing debugging trigger data (to be checked) ROS is going to be redesigned in USC either way, if L1A rate is increased, ROS may become the DDU ROS to DAQ directly=> review how many extra DAQ connections will be needed: no limit means 36 “Slinks” (10 Gbps) instead of present 5-10 Present ROS: 60 boards Future ROS - uTCA based - 60 boards - (2x12) 24 “slow” input links (240 Mbps) - Cheap FPGA - 1 output link ~6 Gbps Not a very expensive board, but we will work on the details when LS1 is more advanced C. F. Bedoya July 26th, 2012 36

RPC constraints RMB Trigger Board x84 DCC x3
The current RPC DAQ system: RMBs (84): readout buffers, pack Link Boards incoming data and send them to the DCCs via the optical Mbit/s DCC – RPC FEDs (3): S-link to the DAQ. These are ECAL boards with our custom firmware. Higher L1A rates or higher latency will require: - RMB: bigger and faster FPGA needed - Optical link bigger bandwidth would have to be used, - DCCs: would have to be replaced with new boards (CMS generic?). Trigger Board x84 DCC But… will RPC trigger electronics remain unchanged until LS3?? x3 C. F. Bedoya December 14th, 2012 37 Thanks to K. Bunkowski 37

CSC constraints "CSC: Is replacing all CFEBs with DCFEBs all that is required?" * Yes (if only L1A latency is increased) * If L1A rate is to be increased, then it will impact also on the SLINK readout. “Is there is any plan to replace present DDU boards with a newer technology?” - Not for the moment - Ideally one could go up to 800 kHz L1A with present L1A rate (with 36 slinks, one per DDU), although it has never been tested. - In addition, this is with present luminosities, no predictions yet to how it will scale with 10 times more. Details of the CSC DDU system: 15 DCFEBs / DDU board. 4 VME crates with 9 DDU boards and 1 Data Concentrator board (DCC) in each crate. 2 SLINK/DCC, meaning 8 SLINKs in total. We are presently at the SLINK bandwidth limit. Our boards are configurable so that we have various ways of adding SLINKs. We can even get rid of the DCC boards and put an SLINK on each DDU giving us a total of 36 SLINKs. (8 times more, 8 times faster, though no estimations on how the data volume will scale) C. F. Bedoya July 26th, 2012 39

CSC constraints Why not build DCFEBs for all CSC?
* Assume Upgrade all Chambers to DCFEBs => 12 million dollars * Manpower: US physicists/engineers on DCFEB project presently 58 & 60 years old New technical experts needed. * We would need to produce more ASICs - Buckeye ASIC 16 channel amplifier shaper - Comparator ASIC 16 channel trigger primitives * At the time of LH-LHC upgrades CSC electronics will be 20 years old! so… If this were done, next bottleneck would be the SLINK readout, ideally one could go to 800 kHz L1A rate, though DDU has not been tested in this conditions, so no straight answer can be given at this point. 15 DCFEBs / DDU board. 4 VME crates with 9 DDU boards and 1 Data Concentrator board (DCC) in each crate. 2 SLINK/DCC, meaning 8 SLINKs in total. We are presently at the SLINK bandwidth limit. Our boards are configurable so that we have various ways of adding SLINKs. We can even get rid of the DCC boards and put an SLINK on each DDU giving us a total of 36 SLINKs. C. F. Bedoya June 29th, 2012 40 Thanks to S. Durkin

CSC constraints MAIN BOTTLENECK CFEB
Analog storage in SCA (Switch Capacitor Array): - 96 strips/CFEB - 96 capacitors/strip - 400 ns strip pulse - Stored until LCT is received - Digitization and readout happens if LCT+L1A coincidence The higher the L1A latency the worst (longer time until digitization can start) The rate and latency limitations come from the SCA overuse probability µsec L1A latency + CLCT rate (poisson statistics) - 26 µsec digitization + L1A rate (queue statistics) The higher the L1A rate the worst (more samples to digitize) Higher detector occupancy (HL-LHC) only emphasizes the problem (higher input rates, higher CLCT rates) (Presently CLCT rate poorly known for LH-LHC ) C. F. Bedoya December 14th, 2012 41 Thanks to S. Durkin

CSC constraints DCFEB (Digital CFEB ME1/1 Upgrade 2013)
Replace Conventional ADC and SCA storage with Flash ADC and Digital Storage - 96 strips/CFEB - Flash ADCs digitize all strips at 40 MHz - FPGA memory used as digital pipeline - Triggered events fiber readout at 2.5 Gbits/s * L1A latency irrelevant (huge FPGA block RAMs): 6, 10, 20 µsec (all fine) * Buffer Overflow depends weakly on L1A rate 1e-05 C. F. Bedoya December 14th, 2012 42 Thanks to S. Durkin

DT constraints 2. Increase trigger rate (200 kHz or 500 kHz or 1 MHz?)
2nd bottleneck : DDU processing time * DDU limit is 250 Mbytes/s * Present event sizes are < 1 kbyte (max 250 kHz L1A?) but event sizes will increase (see next slide) 3rd bottleneck : ROB output link bandwidth * TDCs could be still ok at 1 MHz L1A rate but… * output link maximum bandwidth for a L1A rate of 800 kHz (optimistically)… to be tested C. F. Bedoya June 29th, 2012 44

DT constraints Full readout of your subsystem at the crossing frequency of 40 MHz? * If no event matching is performed in the TDCs maybe we can readout all hits as they arrive * Drift time information referred to the BC0? * Needs more deep thinking and testing - Would like to test if in present ROBs this can be done (without rebuilding them). - Tricky but maybe not impossible - Also, would it be needed? (maybe higher L1A rate is acceptable for ROBs) - If ROBs are to be rebuilt for aging, then it is an interesting option C. F. Bedoya June 29th, 2012 45

Muon constraints summary
Increase of L1A latency (20 us): - Replacement of CSC DCFEBs (~12000 k$ + big trouble) - Replacement of RPC chain (RMB, DCC) (~100 keuros) Increase of L1A rate (1 MHz): - Replacement of CSC DDUs (?) - Replacement of DT ROS and DDUs (~400 keuros?) and >800 kHz likely ROB-ROS link? (big trouble) * Studies are needed to make sure there are no other bottlenecks * Studies are also needed to quantify which L1A rate limit can be reached without modification (maybe 1 MHz L1A rate too much but 800 kHz ok) * Upgrade plans are evolving, some parts may be redesigned either way (likely changing the cost profiles) C. F. Bedoya July 26th, 2012 46

From I. Redondo Muon rate estimations eta 47
C. F. Bedoya December 11th, 2012 47

DT CONCLUSIONS We don´t expect any problem for running present ROBs design with Phase 2 occupancies and 100 kHz L1A rate and 6 us L1A latency With the background rates expected in Phase 2, it is unlikely that we could run at a trigger rate higher than kHz. Latencies of 20 us could likely be achieved, although proper testing should be done. HPTDCs could be operated in continuous mode, which should allow operation with 20 us latency and 1 MHz trigger rate. However, this means no background reduction is possible playing with the time window (no filtering is done, all hits are sent). Therefore, we could start to loose efficiency for background rates larger than Hz/cm2. (This number should also be checked). MB4 rates are too close to this number (27 Hz/cm2 for YB-2 S4 MB4). Any action to place a shielding in the MB4s of the upper sectors or in the MB1s of the external wheels will reduce any possible efficiency drop. Considering the large uncertainties (energy, extrapolation, target luminosity, etc), even if the MB4s can be shielded, replacing the ROBs of the MB1s external wheels with a higher performance board, should also not be discarded C. F. Bedoya December 11th, 2012 48

RMB RPC constraints Exercise: Present system 10GBit/s RMBs Option 1
Thanks to M. Konecki July 26th, 2012 49 Option 1 Option 2

DCC RPC constraints Exercise: 50 Thanks to
M. Konecki December 14th, 2012 50

Total In the order of 100-150 keuros RPC constraints
Total costs of increasing either latency (20 us) or trigger rate (in principle up to 1 MHz, although occupancy vs luminosity needs better studies): Exercise: 20 keuros? In the order of keuros (note: RPC upgrade plans are still to be defined, this is the scenario in which nothing else is changed except L1 latency or rate requirements) Thanks to M. Konecki December 14th, 2012 51

RPC constraints USC UXC
If L1A latency increased or L1A rate increased, we will need to modify: USC * Luckily all in USC… * Mainly mezz and FED UXC Bandwidth to be verified in phase 2, but this is independent on L1A parameters New RMB (Readout Mezzanine Board) mezzanines (84) New Optical links (presently 84 u. 640 Mbps GOL) New DCC cards (Presently 3 u. ECAL DCC with modified firmware) C. F. Bedoya December 14th, 2012 52 Thanks to M. Konecki

CSC constraints IF CFEB SOLVED, DDU SECOND BOTTLENECK (only a problem if L1A rate is increased) CFEB: MAIN BOTTLENECK for latency and L1A rate 400 ns pulses Digitize at 25 ns C. F. Bedoya February 19th, 2013 53 Thanks to S. Durkin

DT CONCLUSIONS 100 kHz and 6 us latency OK without changes
300 kHz and 20 us latency OK but needs further testing 1 MHz and 20 us could still be possible if continuous mode works fine and occupancies don´t grow too much (needs further testing) 1 MHz and 20 us is always possible if all the ROBs are replaced: 1 year shutdown fully DT devoted, 5 MCHF Replacing a fraction of the chambers would also give more margin: YB-/+2 MB1s: 5 months shutdown fully DT devoted, 1 MCHF (Replacing YB-/+2 MB1s and MB4s: ~1 year shutdown fully DT devoted, 2 MCHF) Remember that there are uncertainties in the occupancies expected at double energy which could change this picture. Any action to place a shielding in the MB4s of the upper sectors or in the MB1s of the external wheels will reduce any possible efficiency drop. Considering the large uncertainties (energy, extrapolation, target luminosity, etc), even if the MB4s can be shielded, replacing the ROBs of the MB1s external wheels with a higher performance board seems a good idea C. F. Bedoya December 11th, 2012 54

DT CONCLUSIONS 100 kHz and 6 us latency OK without changes
300 kHz and 20 us latency Should be OK but needs further testing 1 MHz and 20 us could still not be impossible if continuous mode works fine and occupancies don´t grow too much (needs further testing) 1 MHz and 20 us => all ROBs to be replaced: 1-2 years shutdown fully DT devoted, 5 MCHF? 25 us => all ROBs to be replaced: 1-2 years shutdown, 5 MCHF? Replacing a fraction of the chambers would also give more margin: YB-/+2 MB1s: 5 months shutdown fully DT devoted, 1 MCHF (Replacing YB-/+2 MB1s and MB4s: ~1 year shutdown fully DT devoted, 2 MCHF) Remember that there are uncertainties in the occupancies expected at double energy which could change this picture. Any action to place a shielding in the MB4s of the upper sectors or in the MB1s of the external wheels will reduce any possible efficiency drop. Considering the large uncertainties (energy, extrapolation, target luminosity, etc), even if the MB4s can be shielded, replacing the ROBs of the MB1s external wheels with a higher performance board seems a good idea C. F. Bedoya December 11th, 2012 55

CMS DT Phase 2 * ROS will be redesigned between LS1 and LS2.
* Will try to incorporate DDU functionality to remove further bottlenecks * i.e. impact is on the ROB C. F. Bedoya December 11th, 2012 56

Background estimations
Rate outside trains, no muons included (basically neutrons and punchthrough) Big difference between chambers,: - YB-2 S4 MB kHz/TDC channel - YB-/+2 MB1s 12 kHz/TDC channel Uncertainties in scale with energy and effect of measuring inside train 1035 drift (400 ns) background 1035 time window 1.2 us C. F. Bedoya December 11th, 2012 57

Background estimations
* Upper sectors MB4 * Leaks between barrel and endcap in MB1s From G. Masseti C. F. Bedoya December 11th, 2012 58

Impact on the ROB LATENCY impact => L1 buffers
Hits stored in L1buffer until the L1A arrives and trigger matching is performed Occupancy studies => store 12 hits per L1buffer FIFO every 20 us, while they are 256 positions in the FIFO. It seems it should be possible to work with 20 us latency in phase 2 occupancies (Although effect of potential slower matching needs to be tested) LATENCY impact => L1 buffers (slower matching?) C. F. Bedoya December 11th, 2012 59

Impact on the ROB L1A rate impact -Readout FIFO
-Event processing speed -Output link bandwidth Readout protocol is slow: shared among 4 HPTDCs (byte-wise at 20 MHz) It is very slow, this is the main bottleneck, eventually Readout FIFO fills up Preliminary simulations seemed to point that 800 kHz-1 MHz could be ok, but testing at lab with Phase 2 occupancies shows otherwise (at least for some chambers) C. F. Bedoya December 11th, 2012 60

ROB Trigger rate test Test perform on a ROB at lab with fixed trigger rate: <- Phase 2 occupancies? (maybe optimistic?) Therefore, a safe scenario without changes seems could be 300 kHz and 20 us C. F. Bedoya December 11th, 2012 61

Options without replacing ROB?
trigger matching: reduces the payload. (100 kHz L1A rate => one L1A each 10 us with a sampling window of 1 us => we read 10% of the time) At 1 MHz L1A rate => we will be reading 100% of the data, thus trigger matching is an overhead of processing time and bandwidth (headers and trailers) In principle, it is possible to run the HPTDCs in continuous mode: - hits sent as arrive from chambers, - time measurement referred to BC0 Latency and L1A rate becomes irrelevant for the ROB Trigger matching in the new ROS may be possible (needs study and will imply detailed calibrations). Limiting factor is the bandwidth of the readout link, saturation at aprox background 39 Hz/cm2 (MB4s are expected to reach 27 Hz/cm2....) This may work depending on the uncertainty of the background. If it is large, then we start to be inefficient C. F. Bedoya December 11th, 2012 62

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