1. The Cortex-M3/m4 Embedded Systems: Cortex-M3/M4 Instruction Sets
Refer to Chapter 4 in the reference book
“The Definitive Guide the ARM Cortex-M3”
Refer to Chapter 5 in the reference book
“The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors”

2. ARM Instruction Set Architecture
There are quite a lot of instructions in the Cortex-M processors, but there is no need to learn them all in detail
C compilers are good enough to generate efficient code
the free CMSIS-DSP library and various middleware (e.g., software libraries)

3. Assembly Basics The syntax depends on the assembler that you’re using
With the ARM assembler, the common instruction format is as follows
label is optional, used as a reference to an address location
mnemonic is the name of the instruction
The number of operands depends on the type of instruction
Normally, the first operand is the destination of the operation
The text after each semicolon (;) is a comment

4. Assembly Basics Immediate data are usually in the form #number
Define constants using EQU
Use DCB and DCD to define byte-size and word-size variables, respectively
Use of suffixes

5. Using Unified Assembler Language
To allow better portability between architectures, UAL was developed
Using the same syntax for both make it easier to port applications between ARM code and Thumb code
The traditional Thumb syntax can still be used. Note that some of them change APSR without the S suffix
You can specify whether to use Thumb or Thumb-2 instructions by adding suffixes of .N or .W
Note: In most cases, applications will be coded in C, and the C compilers will use 16-bit instructions if possible due to smaller code size

6. Assembly Basics 32-bit Thumb-2 instructions can be half word aligned
Most of the 16-bit instructions can only access registers R0 to R7; 32-bit Thumb-2 instructions do not have this limitation

7. 16-bit Instruction List

8. 16-bit Instruction List

9. 32-bit Instruction List

10. 32-bit Instruction List

11. Moving data within the processor
Between register and register
Between special register and register
Moving an immediate data value into a register
For the Cortex-M4 processor with the floating point unit
Between a register in the core register bank and a register in the floating point unit register bank
Between a floating point system register (such as the FPSCR - Floating point Status and Control Register) and a core register
Move immediate data into a floating point register

12. Between Register and Register
MOV
Move data between registers
MVN
generate the negative value of the original data and move to the destination register

13. Between Special Register and Register
MRS and MSR
Use the instructions MRS and MSR to access special registers
APSR can be accessed with user access level with other special registers only being accessed in privileged mode

14. Between Immediate data to Register
MOV can be used for small values (8 bits or less)
Thumb-2 instructions MOVW and MOVT for larger values
LDR (LDR pseudo-instruction, not the LDR instruction)
A pseudo instruction provided in ARM assembler can be used to load a register with either a 32-bit constant

15. Between Immediate data to Register
LDR can also used to load a register with an address
If the address is a program address value, it will automatically set the LSB to 1
If the address is a data address, LSB will not be changed

16. Memory Access Instructions
LDR and STR
LDR transfers data from memory to registers, and STR transfers data from registers to memory
Be aware of the position of the destination operand

17. Memory Access Instructions
LDM (Load Multiple) and STM (Store Multiple)
Multiple Load and Store operations can be combined into single instructions

18. Memory Access Instructions
“!” in the instruction specifies whether the register Rd should be updated after the instruction is completed
If R8 equals 0x8000
Memory access with pre-indexing
The register holding the memory address is adjusted first and then the memory transfer then takes place with the updated address.

19. Memory Access Instructions
Memory access with post-indexing
The memory transfer is carried out using the base address specified by the register and then update the address register afterward
PUSH and POP

20. Processing Data
Many data operation instructions can have multiple instruction formats
Arithmetic functions, logical operations, reserving bytes in a register, and bit operations
Note that when 16-bit Thumb arithmetic instructions are used the flags in the PSR will be automatically affected.
For 32-bit Thumb-2 instructions, changes of PSR depends on whether the S suffix is used

21. Examples of Arithmetic Instructions
Operation
ADD Rd, Rn, Rm ; Rd = Rn + Rm
ADD Rd, Rm ; Rd = Rd + Rm
ADD Rd, #immed ; Rd = Rd + #immed
ADD operation
ADC Rd, Rn, Rm ; Rd = Rn + Rm + carry
ADC Rd, Rm ; Rd = Rd + Rm + carry
ADC Rd, #immed ; Rd = Rd + #immed + carry
ADD with carry
ADDW Rd, Rn,#immed ; Rd = Rn + #immed
ADD register with 12-bit immediate value
SUB Rd, Rn, Rm ; Rd = Rn – Rm
SUB Rd, #immed ; Rd = Rd – #immed
SUB Rd, Rn,#immed ; Rd = Rn –#immed
SUBTRACT
RSB.W Rd, Rn, #immed ; Rd = #immed –Rn
RSB.W Rd, Rn, Rm ; Rd = Rm - Rn
MUL Rd, Rm ; Rd = Rd * Rm Multiply
MUL.W Rd, Rn, Rm ; Rd = Rn * Rm
Reverse subtract
Multiply
UDIV Rd, Rn, Rm ; Rd = Rn /Rm
SDIV Rd, Rn, Rm ; Rd = Rn /Rm
Unsigned and signed divide

22. Call and Unconditional Branch
B and BX
The most basic branch instructions
BL and BLX
To call a function
Note: In BX instructions, the LSB of the value contained in the register determines the next state (Thumb/ARM) of the processor. In Cortex-M3, since it is always in Thumb state, this bit should be set to 1; otherwise, the program will cause a usage fault exception.

23. Making a Branch Branch using MOV, LDR and POP instructions Note:
1) To make sure that the LSB of the new program counter value is 0x1 (indicating the state of the next instruction is Thumb state)
2) BL instruction will destroy the content of LR. If you need the LR later, you should save the LR before using BL. For example, PUSH {LR}

25. Decisions and Conditional Branches
In the APSR, four of five flags are used for branch decisions

26. Decisions and Conditional Branches
With combinations of the four flags (N, Z, C, and V), 15 branch conditions are defined

27. Decisions and Conditional Branches
Conditional branch instructions
Used in IF-THEN-ELSE structure

28. Several Useful Instructions
MRS and MSR

29. Several Useful Instructions
IF-THEN-ELSE

30. Several Useful Instructions
CBZ and CBNZ
Refer to the reference book for information of other instructions