1. Dominique Gigi CMSweek 6 June 2003
FRL (FED Readout Link)
Overview
Block-diagram
FRL
Transmitter mezzanine
Test setup
Options
8 configurations
Backplane IO
PCI >>> PCI-x
Conclusions
Dominique Gigi CMSweek 6 June 2003

2. Dominique Gigi CMSweek 6 June 2003
Overview
Dominique Gigi CMSweek 6 June 2003

3. Block Diagram Dominique Gigi CMSweek 6 June 2003 64b @ 66 or 100MHz
Commercial Optical Link
Myrinet Lanai X
64kB
IN_1
PCI connector 64-bit
64kB
FRL Function
PCI 66 or
PCI-x 100MHz
IN_2
FPGA
64kB
Bridge
IN_3
FPGA
Memory
4Mbytes
Compact PCI Back-plane
Compact PCI
32-bit 33MHz
64kB
IN_4
Dominique Gigi CMSweek 6 June 2003

4. Transmitter Mezzanine
SLink64 protocol
LVDS
Altera
ACEX
LVDS
Generate 3 frequencies:
40MHz from 10 to 15 meters
60MHz from 5 to 10 meters
80MHz <= 5 meters
1 switch to choose the frequency
Dominique Gigi CMSweek 6 June 2003

5. Dominique Gigi CMSweek 6 June 2003
Test setup
Myrinet protocol emulator
Acquisition (64b-66MHz)
LVDS 640MB/s
FRL
Spy mode (Event_ID# 1 to 1024)
FED emulator
PCI to CompactPCI PC
Dominique Gigi CMSweek 6 June 2003

6. Test setup (data flow) Dominique Gigi CMSweek 6 June 2003 FED_emu1
Event_ID
Event_size (bytes)
BX_id
Source#
Time (x100ns) before next event
FED_emu1
(GIII)
FRL
PCI
Myr_protocol_emu
(GIII) H
FRL_Myrinet
protocol
Event(t+1) T
Event(t) H
Event(t-1) H T
WAIT
WAIT H T
64kB
LVDS
Packet
size
Source#
Event_ID H H
Packet#
FED2
FRL
FPGA
FED1
reserved
Pack. size
FED_emu2
(GIII)
reserved
64kB
Spy mode
From 1 to 2 M event descriptors
Using SDRAM memory
Host_PC
Bridge
LVDS
ZBT
memory
PC memory
Data block size
Event(t+1) T
Event(t) H
FED-kit
WAIT
WAIT
Event(t-1)
Block0
Block1 H T H
Block2
Block3
PCI to CPCI link
Block4
Block5 T
Block6
Block7
Block8
Block9
Blockn
WC_E1
WC_E0
Dominique Gigi CMSweek 6 June 2003

7. FPGA Configuration Dominique Gigi CMSweek 6 June 2003 Flash memory
Add[2..0]
FRL diagnostic
111
FRL (Evt generator)
110
FRL (Evt memory)
101
Bus to FPGA
configuration
100
011
010
001
FRL with Input
000 (configuration by default POWER ON)
Accessed through
PCI Bridge configuration
Signal to
reconfigure FPGA
128 ms to load a design from Flash to FPGA
NB: Bridge design (EEPROM) and FRL (FLASH) designs
can be downloaded through the PCI Bridge configuration.
Dominique Gigi CMSweek 6 June 2003

8. Dominique Gigi CMSweek 6 June 2003
IO's backplane
It’s not a bus each FRL has its individual pins
Lemo
16 IO’s FRL
15 IO’s Bridge
5 v
3.3v
-12v
+12v
GND
Ethernet
Compact PCI backplane
CompactPCI bus
Dominique Gigi CMSweek 6 June 2003

9. PCI (66MHz) ---- PCI-x (100MHz)
-Access to the LanaiX
configuration
-Pending
data transfer
PCI-x bus
64-bit
100 MHz
Bridge
Convert
PCI access to
PCI-x access
AD[63..0]
FRAME
IRDY
TRDY
Addr
Data
Attr
Dominique Gigi CMSweek 6 June 2003

10. Setup to test production
4 points to control:
Inputs (Connectors, FIFO,LVDS,FPGA)
PCI bus
ZBT memory (data, address, control)
JTAG
One PC controls 16 FRLs (CompactPCI backplane)
GIII generates events and receives them through PCI to control data and header  registers report errors
ZBT is tested through the SPY mode application
JTAG is tested with JAM-Player (adapted by Christoph) access the JTAG chain through PCI bus
Dominique Gigi CMSweek 6 June 2003

11. Dominique Gigi CMSweek 6 June 2003
Conclusions
PCI-x protocol is tested (without data transfer; single access)
The 2 Inputs were debugged
ZBT memory access
Start the setup implementation for test production
Pending
transfer data with PCI-x protocol to Myrinet LanaiX
merge function (logic – no hardware)
CRC implementation (FED_emu + check inside FRL)
Dominique Gigi CMSweek 6 June 2003