1. A 12 µm pixel pitch 3D MAPS with delayed and full serial readout for the innermost layer of ILC vertex detector Yunan Fu (on behalf of the CMOS Sensor Group of IPHC)
Outline
Subreticule B highlights
Delayed R.O architecture for the ILC vertex detector
CAIRN-3
Pixel design
Test plan
Summary and perspectives
1, I am pleased to have the opportunity to present another 3D CMOS MAPS design on behalf of the CMOS sensor group of IPHC,
2, During the next ten munities, I shall give information about the work what we have done and to present a plan for future developments
3, The subject of this presentation is **** Let's briefly look at the outline of this presentation.
First of all, ****
Secondly, ****in this part, I will explain the reason why a 12 um pixel pitch is chosen for the ILC physics experiment.
Then I will continue to describe our design in further detail.
Another is ****
Finally. ****

2. Subreticule B highlights1 2 3 3’
Digital Tier
Analog Tier
B Left (BL) B Right (BR)
Subcircuit (3) – CAIRN-3 (IPHC, Strasbourg)
256 x 96 array with a 12 x 24 µm rectangular pixel.
Sensor, Preamp (only NMOS) & Shaper , zero-crossing Discriminator in each analog pixel.
5-bit TDC & the 2nd hit flag circuitry in each digital pixel.
Serial transmitter (8b/10b encoder & two types of PLLs)
10-bit low power consumption DAC
Test circuitry for the front-end electronics.
Future goal: Separating analog tier into two tiers and reduce the
pixel size to 12 x 12 µm.
Subreticule B – Three subcircuits:
1) 2 separate memory cores (CMP)
2) MAPS for ILC (IRFU, IPHC)
42x240 array, 20 µm pixel MAPS operating in rolling shutter mode (80 ns/row).
3) MAPS for ILC (IPHC)
256 x96 array, 12 x 24 µm rectangular pixel MAPS operating in Delayed readout mode.
Future goal: 7-bit TDC & 2nd hit flag in a 12 µm digital pixel
1. There are three kinds of sub-circuit in the sub-reticule B, Our design is sub-circuit 3, We have designed ****
2. Each analog pixel contains****; in addition, a 5-bit TDC ****
3. Currently, at the periphery of the pixel matrix, the chip incorporates test auxiliary /ɔ:g'ziljəri/ blocks such as PLL, 8b/10b encoder interface, 10 bit low power DAC, ****
4. In near future, the next step is to separate analog tier into ****
a 7-bit TDC and 2nd hit flag will be implemented in the same feature size pixel in order to meet the ILC physics requirements.
18/03/ D workshop (Marseilles)
IPHC

3. Delayed R.O. Architecture for the ILC vertex detector
Try 3D architecture based on a 12 µm pixel pitch, motivated by :
<3 µm single point resolution with binary output
Probability to fire a pixel more than once << 10%
Adapted to the ILC beam time (detection phase =1 ms, readout phase~199 ms)
12 µm pitch pixel with a 2nd hit flag operating in delayed R.O mode
sp >~ 2.5 μm, Probability to fire a pixel more than once ~5%
Explore 3DIT advantages  Split signal collection and processing functionalities
Tier 1 : Process adapted to charge collection, high or normal res EPI (ex. XFAB process)
Tier 2 : Analogue tier: Shaper & discriminator
Tier 3 : Digital tier: 7-bit TDC + 2nd hit flag using an advanced CMOS process (ex.<< 100 nm).
2 tiers technology  combine charge collection tier and analogue tier together
12 x 24 µm rectangular pixel for the first prototype step
Tier 1- A : Sensing diode & preamplifier (only NMOS)
Tier 1- B : Shaper & discriminator
Tier : 5-bit TDC & 2nd hit flag (Tint = 31 µs)
Propose
Future
Detector diode +
Preamplifier
(DP)
Shaper +
Discriminator
(SD)
5-bit time stamping capture +
Flag the 2nd Hit circuitry
(TS&R.O) DP
Future
TSV SD
1. In order to define the pixel size for the innermost layer of the ILC vertex detector, the following point have to be considered;
a) single point resolution with binary readout is less than 3 µm (micro meter)
b)**** is much less than 10 percent ,
therefore, we propose the 12 µm pixel because
**** b) **** and the second hit should come up near the end of the train in most cases, time stamping is less necessary for the second hit , an 2nd hit flag displays whether the pixel is fired a second time or not is enough.
For the sake of power consumption, the tiers feature a delayed readout architecture, adapted to ****
2. So we suppose an ideal 3-tier 3D CMOS MAPS for ****
Tier1 each pixel has sensing element and preamplifier, ****
Tier2 **** Tier3****
3. However, the first 3D submission is limited to two tiers, so for the first step, (kəm'bain)
Due to the constraint of the area only 5-bit time stamping **** is implemented.
TS&R.O
Now
12 µm
12 µm
18/03/ D workshop (Marseilles)
IPHC

4. CAIRN-3 Digital Pixels Analog Pixels
PLLs (10 MHz MHz)
Loop fliter
- 2-order loop fliter
- Parameter programable
loop fliter
Testablity (FEE):
DC feedback
- Con.time MOS Res
- Time-invariant shaper
Digital
Pixels
Bias voltage generator
- For the sake of power,
It adaptes to the ILC
beam time.
5-bit Gray counters
Snake-like structure
Readout
Clock tree
Pixel array: 128 x 96
In each pixel (24X12 µm) :
- Sensor
- Front-end electronics
Pixel array: 256 x 96
- 5-bit time stamping capture
- the 2nd hit Flag
Analog
Pixels
Pixel array: 128 x 96
In each pixel (24X12 µm) :
- Calibrated test circuit
- Front-end electronics
HIT encoder
7-bit digital signal
(200 KHz)
The main purpose of this chip is to validate the concept of 3D CMOS MAPS, This chip includes two tier. The analog tier is divided into two sub-arrays. One part contains the charge collecting diode, while the other part contains the analog FEE with a calibration structure for emulating hits. In the digital TIER, each ****. During the detection mode, each digital pixel latches ITS time stamping information of ***, and during readout mode, the matrix of pixels forms a long shift register (snake-like structure) where data are read out successively.
At the peripheral (pə'rifərəl) of the chip, a bias generator sets the reference voltage to FEE. Time stamping signals come from a 5-bit gray counter. Hit encoder will encode 5-bit time stamping and 2nd hit flag, and data are sent to 8b/10b encoder at 200 k Hz ['hə:ts]. Full serial readout ****
3. PLL, FEE and DAC.
8b/10b encoder
-Full serial readout (100 MHz)
10-bit DAC
- Test auxiliary block
18/03/ D workshop (Marseilles)
IPHC

5. Pixel design
READ_test
Scan flip flop D TI TE
CLK Q
DO<5>
DI<5>
5 Scan flip flops
DO<4:0>
DI<4:0>
MUX
DO<4:2>
DO<1>
DO<0>
Vth
GND
Vref
G~5
Shaper
Discriminator S1 S2
DC feedback
CS Amp
OUT
5 BITS TIME STAMP
Flag Bit
5-Bit TDC
READ
Power_on
MOSCAP
Amp
Analogue Pixel
Digital Pixel
In the analog pixel, there are diodes and CS amp, the gain is appr 5; in other part****, At the first reset phase,S2 ****; At the detection phase,S1
2.When the pixel is fired at the first time, Flag bit ****, TS****; During the acquisition mode.
When the second hit is arrived, Flag bit****, TS**** because the five scan flip flops are only sensitive to the rising edge of the CLK signal.
At the readout phase,
3, For the digital pixel cells, testability should be considered independently of signal of analog tier, a test structure is designed to emulate hits. So the clock signal is used to inject a pulse instead of hits.
Test
Work
18/03/ D workshop (Marseilles)
IPHC

6. It is worth mentioning that ****.
Test Plan
Laboratory tests :
Test PLLs / DAC circuitry independently.
Test front-end electronics.
Validation design of the digital pixel in emulating hits and shift readout test mode.
Validation of 8b/10b interface.
Fe55 test in the Laboratory :
Double-sided bonding
Devices
top *A *D D* A*
Flip
Flip D*
10 µm
Circuit board *A *D
Horz D* A* *A
700 µm *A
bottom D*
Bonding
TOP Wafer
Mirror PADs
Bonding
BOM Wafer A*
top
It is worth mentioning that ****.
The reticule hosts top-tier chips and bottom-tier chips on its left and right side, after flipping one wafer over bottom wafer.
one with the analog tier being thinned and another one with the digital tier being thinned.
Double-sided bonding helps us to realize this idea. A*
10 µm *D *A *D *A *D *D
700 µm
Circuit board
Mov
Devices
bottom *A *D
Horz *A *D
A----Analog tier
D----Digital tier
18/03/ D workshop (Marseilles)
IPHC

7. Summary and perspectives
The 3D 2-tier CMOS MAPS with delayed and full serial readout architecture has been designed and being fabricated.
Small pitch pixel (12 x24 µm): Sensor, front-end electronics and 5-bit TDC (Tint=31µs).
Full serial read-out speed : ~100 MHz.
Test auxiliary blocks such as PLLs, DAC, FEE, 8b/10b interface.
PCB boards have been designed and fabricated.
Future development :
Small feature pitch pixel for 3D MAPS
Use best suited technology adapted to charge collection (ex.XFAB)
A 12 µm pixel MAPS with 7-bit time stamping, 2nd hit marker (digital process << 100 nm).
3D CMOS Rolling Shutter Mode MAPS with fast digital readout (R&D in progress).
- Low power dispersion , suitable for large size imager.
- In order to further improve the single point resolution, time resolution and save power consumption.
Tier-1 : Sensor + preamplifier + amplifier ( G~500 µV/e-)
Tier-2 : 4-bit RS pixel-level ADC with offset cancellation circuitry ( LSB ~ noise level)
Tier-3 : fast pipeline readout with data sparsification circuitry
See talk of W. Dulinski
See talk of Yavuz DEGERLI
18/03/ D workshop (Marseilles)
IPHC

8. 18/03/2010 3D workshop (Marseilles)
IPHC

9. A vertically integrated 3D CMOS MAPS with fast pipeline digital readout
3D CMOS MAPS with fast pipeline digital readout (R&D in progress).
Tier 1: Sensor + preamplifier + amplifier (G~500 µV/e-)
Tier 2: 4-bit pixel-level ADC with offset cancellation circuitry (1LSB ~ noise level)
Tier 3: Fast pipeline readout with data sparisification
Sensor & Amp
Shaper & Dis.
7-bit TDC &
2nd Hit Marker Bit
12 µm
TSV
Using advanced technology (<<100 nm)
1. Tint ~ 7.8 µs
Chartered 130 nm
2. sp ~ 2.8 µm
Solution 1
7-bit TDC &
2nd Hit Marker Bit
5-bit TDC &
2nd Hit Marker Bit
24 µm
12 µm
12 µm
3. Delayed R.O
12 µm
Future goal
12 µm
Solution 2
Low power
Rolling shutter mode
Token
Data sparisifaction
18 µm
18 µm
Sensor & Preamp
( 500 µV/e )
1. Tint ~ 7.0 µs
Token
sp ~ 2.0 µm
2. sp ~ 2.0 µm
Tint ~ 7.0 µs
TSV
4-bit Pixel-ADC
( 20 µW / Pixel )
3. Rolling shutter
Increasing the pixel pitch (18 µm)
18 µm
Token
18 µm
Pipeline Rolling Shutter
18/03/ D workshop (Marseilles)
IPHC