1. PRALLEL CLIPPER
The parallel configuration is defined as while the parallel variety has the diode in a branch parallel to the load.

3. EXAMPLE
Determine the output voltage for the network shown in the fig.

4. SOLUTION
Diode will be on for the –ve half cycle .So the effective circuit is shown in the fig.

5. SOLUTION Apply Id = 0, Vd =0 to get transition voltage so that
Vi – IdR – 4V =0
Vi – 0R – 4V =0
Vi = 4V is transition voltage.

6. SOLUTION hence for the positive half cycle so that VL = V0
VL = 16 Volts.

7. EXAMPLE
Consider in previous example the diode is silicon diode and draw its output.

8. SOLUTION
The diode will be on for the negative half cycle. Apply Id=0 ,Vd = 0.7 to get transition voltage
Vi + VT – V =0
Vi = V – VT
=4 – 0.7 = 3.3 V

9. SOLUTION
3.3 is the transition voltage will be 4V, hence for positive half cycle
VL = V0
V0 = 16V

11. CLAMPERS
These are the circuits which clamp the input signal to a different level depending upon the configuration of the clamper circuit. For carrying out analysis following points to be remember

12. CLAMPERS
The total swing of the output is equal to the total swing of the input signal.
Start the analysis by considering that part of the input which will forward bias the diode.
During the period, the diode is ‘ON’, assume that the capacitor will charge up instantaneously to a

13. CLAMPERS level determined by the network.
(4) During the period for which the diode id ‘OFF’ assume that capacitor will hold its charge.
(5) Throughout the analysis keep complete awareness of the polarity for V0, So that the proper value of Vo is determined.

14. EXAMPLE
Determine v0 for the network shown in the fig.

15. SOLUTION
Our analysis will begin at time t1 to t2 .our circuit will behave as shown in the fig. Applying KVL to input loop
-20 + Vc – 5 =0
Vc = 25V

16. SOLUTION
The capacitor will therefore charge up to 25V. In this case the resistor will not be shorted by the diode, but a Thevenin’s equivalent circuit for that portion of the

17. SOLUTION
network which includes the battery and resistor will result in Rth = 0, with Eth = V = 5V. For the period t2 to t3 the circuit is shown in the fig.

18. SOLUTION
KVL across the outer loop
– Vo = 0
And
Vo = 35V

19. SOLUTION
The time constant of the discharging network of fig. is determined by the product of RC and has magnitude
T = RC
= 0.01S

20. The output wave form will get the shape as

21. EXAMPLE
Repeat the previous example using silicon diode with VT = 0.7V

22. SOLUTION
For the short circuit state the network now takes the appearance of the fig. and V0 can be determined by KVL in the output section

23. SOLUTION
+5 – 0.7 – V0 = 0
V0 = 4.3V

24. SOLUTION For the input section KVL will result in -20 +Vc + 0.7 – 5 =0
Vc =25 – 0.7 =24.3V

25. SOLUTION
For the period t2 to t3 the network will now appear as in fig. By KVL
– V0 = 0
V0 = 34.3V