1. Combined SR/SP UF Fits all of previous SP board logic! Main FPGA
Phi Global LUT
DC-DC Converter
Eta Global LUT
Phi Local LUT
EEPROM
Fits all of previous SP board logic!
Stiffener
Indicators
FM RJ45
VME/CCB FPGA
TLK2501 Transceiver
From CCB
Front FPGA
To MS
DDU FPGA
PT LUT
Main FPGA
Optical Transceivers (16)
MB1-to-SP
Mezzanine Card
ME1-to-DT
SRAM

2. SR/SP Design Status Schematics completed: Layout underway: UF
Sector Receiver Front FPGAs (5 total): XC2V1000-FF896C
Sector Processor Main FPGA: XC2V4000-FF1152C
Placed on mezzanine card with 780 I/O signals
Uses “Verilog++” to describe firmware, validated in ORCA
VME & control interface FPGA: XC2V250-FG456C
DAQ Interface FPGA: XC2V250-FG456C
SRAM: 51 SRAM chips (>64MB) for Look-up functionality
Layout underway:
Mezzanine board complete
Main board routing:
Problems encountered with PNPI routing
Sent to outside vendor for completion

3. SR/SP Schedule Main board: Mezzanine card Track-Finder crate backplane
Routing sent 1 Nov. ‘02, expect 6 week delivery
Fabrication and assembly , expect 3 weeks
Ready for test mid to late January
Mezzanine card
Routing complete
Fabrication and assembly to take place in parallel
Track-Finder crate backplane
Schematics done
Routing and fabrication to take place in parallel
Firmware
SP main trigger logic done
SR, VME interface, DAQ interface to be done in parallel