1. Each I/O pin may be configured as either input or output.
EP600
EP600 is a 24-pin device, and has 4 inputs, 2 dedicated clock inputs, and 16 I/O pins.
Each I/O pin may be configured as either input or output.
EP600 has two important architectural features:
It contains Programmable flip-flops, each of which can be configured as D, T, JK, or SR.
Each flip-flop can be triggered by an asynchronous clock signal generated by a dedicated product term, or by the clock signal applied via the dedicated input.

2. EP600 consists 16 macrocells.
EP600 Macrocell
EP600 consists 16 macrocells.
Each macrocell has 40-input/10-output programmable AND array (i.e., it has 10 product terms).
Out of 10 product terms, 8 product terms are used to implement the excitation equations for the flip-flop in the macrocell’s.
In the remaining 2 product terms, 1 is dedicated to control the clear input of the flip-flop, and the other is used for output enable/gated clock implementation.
Since the flip-flop within the architectural control block of a macrocell is programmable; it can be programmed by a single EPROM cell to operate as a D or a T flip-flop.
The T flip-flop is used to perform the JK function by adding 2 AND gates, an OR gate and an inverter.

3. JK flip-flop constructed from T flip-flop

4. EP600 Macrocell
When it is configured as D or T, the 8 product terms of the AND array are ORed together to form the input to the flip-flop.
If it is configured as JK or SR, these 8 product terms are fed via an OR gate to one input of the flip-flop, and the remaining product terms (2 product terms) are fed via OR gate to the other input of the flip-flop.
Like in EP300 and EP320, each I/O pin in an EP600 can be configured to provide a combinational output or registered output with or without feedback, and also as an input.

5. D and T flip-flops

6. JK and SR flip-flops

7. EP600 Clocking Schemes

8. EP600 Clocking Schemes
The EP600 has two separate clock inputs:
One provides clock signals to the flip-flops associated with macrocells 1 through 8, and
Other provides clock signals to flip-flops associated with macrocells 9 through 16.
By programming an EPROM bit in the device, the designer can select either the dedicated product term in a macrocell for individual clock of its flip-flop, or the clock signal synchronous with other macrocells.
In synchronous clocking, the EPROM bit is programmed such that the multiplexer transfers the dedicated product term to the enable input of the tri-state buffer at the output pin of the macrocell.

9. EP600 Clocking Schemes
The multiplexer also connects the dedicated clock input to the corresponding input of the flip-flop.
Thus the flip-flop changes its state in synchronization with flip-flops in other macrocells.
In asynchronous clocking, the EPROM bit programmed such that the enable input of the tri-state buffer is connected to the Vcc.
And the output of the AND gate is connected to the clock input of the flip-flop.
Thus, the output buffer is permanently enabled and the flip-flop is triggered by a product term (i.e., asynchronous clocking)
In the erased state of the EP600, the EPROM bits are set such that synchronous clocking is automatically selected and output buffers are disabled.

10. EP900 is architecturally similar to EP600.
It operates with the maximum clock speed of 33.3MHz and is significantly slower than EP600.
The power dissipation of EP900 is twice to that of EP600.
It offers up to 38 inputs and 24 outputs in a 24 pin package.
It has 24 macrocells which have similar features as those in EP600.
It has input NAND gates compared to 716 in EP600.