1. New 500 MSa/s 12 bit
FADC in VME
Sangyeol Kim
Notice Co., Ltd.

2. History of DMRC Flash ADC board – 1st generation
500 MSa/s 8 bit
150 MHz analog BW
2 channels / board
- Direct conversion(TDA8718)
External clock (500 MHz)
PECL interface
512 kbyte data buffer / ch
Trigger in / out
VME A32/D32
VME 6U size
Used from 2003(?) to 2005(?)

3. History of DMRC Flash ADC board – 2nd generation
400 MSa/s 10 bit
200 MHz analog BW
4 channels / board
- Interleaved conversion(4x AD9215)
Local oscillator (50 MHz)
LVTTL interface
4 Mbyte data buffer / ch
Trigger in / out
VME A32/D16
VME 6U size
Used from 2006(?) to 2009(?)

4. FADC board structure

5. Basics of FADC - sampling
FADC samples point?

6. Basics of FADC
Bits, sampling rate & BW

7. Basics of FADC - interleaving

8. Problem with interleaving? Gain, offset & timing mismatch

9. ADC comparison – Texas Instruments
part
ADC#
S.R.
ENOB
P.C.
price
ADS5463 1
500
10.5
2250
167.20
ADS6129 2
250
11.4
687
73.75
ADS6215 4
125
417
34.40
ADS6122 8 65
11.6
285
15.00 …
ADS7886
512
11.5
3.9
1.70

10. DMRC Flash ADC board – next generation
12 bit? (Sunkee’s law? :
# of bits in DMRC FADC has increased by 2 every four years.)
Sampling rate : 400 or 500 MSa/s?
Analog bandwidth : half of the sampling rate
Data buffer depth : more than 1 ms ( > 500k samples)
Readout rate?
Trigger scheme and timing synchronization.
Stick to VME?

11. 500 MSa/s 12 bit FADC – prototype FADC for JPARC experiments
almost identical architecture to 2nd one
500 MSa/s 12 bit
250 MHz analog BW
4 channels / board
- Interleaved conversion(4x ADS6125)
Local oscillator (62.5 MHz)
LVTTL interface
4 Mbyte data buffer / ch
Trigger in / out
VME A32/D16
VME 6U size
Used for JPARC?