1. DSP Based Electromechanical Motion Control
Unit 1
R. Anil Kumar GRIET

2. R. Anil Kumar GRIET

3. Introduction DSP Controller discussed here is TMS320LF2407
LF2407 Combines powerful CPU with on-chip memory and peripherals
It offers 40 Million Instructions Per Second(MIPS)
This helps in applications such as notch filters or sensor less motor control algorithms where a large amount of calculations must be computed quickly
Their applications range from analog to digital conversion to pulse width modulation generation
R. Anil Kumar GRIET

4. LF2407 Peripheral Set The Event Manager (A and B)
General Purpose(GP) Timers
PWM generators for digital motor control
ADC
Controller Area Network (CAN) interface
Serial Peripheral Interface (SPI)- synchronous serial port
Serial Communication Interface (SCI)- asynchronous serial port
GPIO bidirectional pins
Watchdog Timer
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5. Brief Introduction to Peripherals
The following are integrated onto the LF2407 chip
Event Managers (EVA, EVB)
most important in digital motor control
It has necessary functions needed to control electromechanical devices
Each EV has functional “blocks” including
Timers, Comparators, Capture units for triggering on an event, PWM Logic circuits, quadrature-encoder-pulse(QEP) circuits and interrupt logic.
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6. Peripherals Analog-To-Digital Converter(ADC)
Used when external analog signal needs to be sampled and converted to digital number
Applications range from using in digital notch filer algorithm to monitoring the motor performance
Used in motor control applications, as it allows current sensing using a shunt resistor instead of expensive current sensor
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7. Peripherals The Control Area Network (CAN) Module
It is useful for specific applications, i.e. used for multi-master serial communications between external hardware.
It has high level of date integrity
It is ideal for operations in noisy environment such as in an automobile or industrial environments that require reliable communcation and data integrity
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8. Peripherals Serial Peripheral Interface (SPI)
It is high-speed synchronous communication port that is mainly used for communicating between DSP and external peripherals/or with other DSP
Typical use is communication with external shift registers, display drivers or ADC’s
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9. Peripherals Serial Communication Interface (SCI)
It is an asynchronous communication port.
It supports asynchronous serial (UART) digital communication between the CPU and other asynchronous peripherals that use standard NRZ (Non-return-to-zero) format.
It is useful in communication between external device and DSP
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10. Peripherals Watchdog Timer (WD)
It monitors software and hardware operations and asserts a system reset when its internal counter overflows
If CPU gets disrupted watchdog will generate a system reset
If software enters a endless loop WD timer will over flow and DSP reset will occur
Most error conditions that temporarily disrupt chip operation can be cleared by WD function and thus increases the reliability of the CPU ensuring system integrity
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11. Peripherals General Purpose Bi-directional Digital I/O (GPIO) Pins:
As there are finite number of pins among which many are multiplexed to either their primary function or secondary GPIO function.
GPIO is very useful as a means of controlling the functionality of pins
Also provides another method to input or output data to and from the device.
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12. Peripherals
General Purpose Bi-directional Digital I/O (GPIO) Pins: Contd…
It has two types of registers
I/O MUX Control Registers (MCRx)-used to control multiplexer selection that chooses between the primary function of pin or general purpose I/O function
Data and Direction Control Register(PxDATDIR)-used to control data and data direction of Bi-directional I/O pins
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13. Peripherals Joint Test Action Group(JTAG) Port:
It provides a standard method for interfacing DSP controller for emulation and development
XDS510PP provides connection between the JTAG module on LF2407 and computer
JTAG module allows PC to take full control over DSP while CC Studio is running
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14. Peripherals Phase Locked Loop (PLL) Clock Module
It is basically an input clock multiplier that allows the user to control the input clocking frequency to the DSP Core.
A clock reference (can oscillator) is generated which is fed into LF2407 and is multiplied or divided by PLL.
This new clock signal is used to clock DSP core
LF2407’s PLL allows user to select multiplication factor ranging from 0.5X to 4X that of external clock signal (4X is default PLL Value).
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15. Peripherals
Memory Allocation Spaces: it has 3 different allocations of memory
Data:
- used for program calculations, look-up tables and any other memory used by algorithm
- it can be in the form of on-chip RAM or external RAM
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16. Peripherals Memory Allocation Spaces: Contd… Program memory:
- it is a location of user’s program code
- on LF2407 it is either mapped to
off-chip’s RAM MP/MC-pin=1
on-chip flash memory---MP/MC-pin=0,
Depending on logic value of MP/MC-pin
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17. Peripherals Memory Allocation Spaces: Contd… I/O memory space:
- it is virtual memory address used to output data to peripherals external to LF2407
- Ex: DAC on Spectrum Digital evaluation module is accessed with I/O memory. If one desires to output data to DAC, data is simply is sent to configured address of I/O space with “OUT” command
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18. Types of Physical Memory
Random Access Memory (RAM):
LF2407 has 544 words of 16 bits each in the on-chip DARAM, 2K of SARAM
544 words are partitioned into 3 blocks:B0,B1,B2
B0 different from B1 and B2,
B0 is configured as Data Memory and hence primarily used to hold data, it can also be configured as Program Memory
B1 and B2 are allocated for use only as data memory
B0 configured as Data if core level bit “CNF=0”
B0 configured as Program if core level bit “CNF=0”
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19. Types of Physical Memory
Non-Volatile Flash Memory
LF2407 contains 32K of on-chip flash memory (MP/MC-pin=0)
Flash memory provides a permanent location to store code that is unaffected during power loss
It is electronically programmable and erasable
The on-chip flash is used where DSP program needs to be tested, provided JTAG connection is not practical
Usually external RAM is used instead of flash for code development due to fact that a “flash programming” routine must be performed to flash code into the flash memory
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20. C2xx DSP CPU and Instruction Set
Introduction to C2xx DSP core and Code Generation
C2xx DSP core is heart of LF2407
It is 16-bit processor
It is like CPU in personal computer
It has its own native instruction set of assembly mnemonics
LF2407 DSP consists of C2xx Core plus many peripherals such as Event Managers, ADC etc.
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

21. C2xx DSP CPU and Instruction Set
Components of C2xx DSP Core
It consists of
A 32-bit central arithmetic logic unit (CALU)
A 32-bit Accumulator (frequently used in programs)
I/O data scaling shifters for CALU
A (16bit-by-16bit) multiplier
A Product-scaling shifter
Eight auxiliary registers (AR0-AR7) and auxiliary register arithmetic unit (ARAU)
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

22. Components of C2xx DSP Core
Central Arithmetic Logic Unit (CALU)
It performs 2’s-complement arithmetic using the 32-bit CALU.
The CALU uses 16-bit words taken from data memory, derived from an immediate instruction
CALU can also perform Boolean operations
CALU is transparent to user, i.e. if arithmetic command is used , the user only needs to write the command and later read output from appropriate register
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

23. Components of C2xx DSP Core
Accumulator
Accumulator stores output from CALU and also serves as another input to CALU.
It has 32 bits wide, divided into 2 sections each of 16 bits.
Assembly language instructions are provided for storing high and low order accumulator words to data memory
In most cases, it is written to and read from directly by user code via assembly commands.
In some instances it is also a “transparent” to user.
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

24. Components of C2xx DSP Core
Scale shifters:
It has 3-32 bit shifters that allow for scaling, bit extraction, extended arithmetic, and overflow-prevention operations.
It uses possible commands to shift data left or right
It is also “transparent” to user
There are three shifters used in C2xx core
Input data scaling shifter (Input Shifter)
Output data scaling shifter (Output Shifter)
Product-scaling shifter (Product Shifter)
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

25. Components of C2xx DSP Core
Scale shifters:
Input data scaling shifter (Input Shifter):
This shifter left-shifts 16-bit input data by 0 to 16 bits to align data to 32 bit input of CALU
Ex: say command “ADD 300h, 5”, the input shifter, first shifts the data in memory address “300h” to the left by five places before it is added to the contents of accumulator
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

26. Components of C2xx DSP Core
Scale shifters:
Output data scaling shifter (Input Shifter):
This shifter left-shifts data from the accumulator by 0 to 7 bits before the output is stored to data memory
Content of accumulator remains unchanged
Ex: say command “SACL 300h,4”, output shifter first shifts contents of accumulator to left by 4 places before it is stored to the memory address “300h”.
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

27. Components of C2xx DSP Core
Scale shifters:
Product-scaling shifter (Product Shifter):
It receives the output of the multiplier
It shifts the output of the PREG before output is sent to input of CALU
It has 4 shift modes
- no shift - left shift by one bit
- left shift by 4 bits - right shift by 6 bits
above are useful for performing multiply/accumulate operations, fractional arithmetic or justifying fractional products.
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

28. Components of C2xx DSP Core
Multiplier:
It performs 16-bit 2’s complement multiplication and creates a 32-bit result
C2xx also uses 16-bit temporary register (TREG) and 32-bit product register (PREG)
The output of multiply is stored in the PREG
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

29. Components of C2xx DSP Core
Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers:
It generates data memory addresses when an instruction uses indirect addressing to access data memory.
Eight auxiliary registers: AR0 through AR7
Each loaded with 16-bit value
These are mainly used as “pointers”
The auxiliary register pointer (ARP) embedded in status register ST0 references the auxiliary register.
The status registers ST0 and ST1 are core level registers where Data Page (DP) and ARP values are located
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

30. Mapping External Devices C2xx core and Peripheral Interface
C2xx needs a way to read and write to different peripherals
Each peripheral is mapped to corresponding block of data memory addresses
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

31. System Configuration Registers
System Control and Status Register 1 (SCSR1)-Address 07018h
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

32. System Configuration Registers
System Control and Status Register 2 (SCSR2)-Address 07019h
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

33. Memory R. Anil Kumar GRIET
Memory Blocks and Types
LF2407 has bit words of DARAM divided into three main blocks B0, B1,B2
It also has bit words of SARAM
DARAM- reads and writes twice as fast as SARAM
In addition to RAM there is also flash memory
Flash memory is written by “flashing” the memory which can only be done manually.
Memory R. Anil Kumar GRIET

34. Components of C2xx DSP Core
Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers:
It generates data memory addresses when an instruction uses indirect addressing to access data memory.
Eight auxiliary registers: AR0 through AR7
Each loaded with 16-bit value
These are mainly used as “pointers”
The auxiliary register pointer (ARP) embedded in status register ST0 references the auxiliary register.
The status registers ST0 and ST1 are core level registers where Data Page (DP) and ARP values are located
C2xx DSP CPU and Instruction Set R. Anil Kumar GRIET

35. Memory R. Anil Kumar GRIET
Memory based allocation
Two ways of using physical memory- storing a program and storing a data
Program memory is written to when a program is loaded into LF2407
Data memory is written to during execution of a program (program might use data memory as temporary storage for calculation variables and results)
B1 and B2- Data memory
B0 either maps Data or Program (CNF bit in Status Register ST1=0 Data, if it is ST1=1 Program
Memory R. Anil Kumar GRIET

36. Memory R. Anil Kumar GRIET
Memory based allocation
Two ways of using physical memory- storing a program and storing a data
Program memory is written to when a program is loaded into LF2407
Data memory is written to during execution of a program (program might use data memory as temporary storage for calculation variables and results)
B1 and B2- Data memory
B0 either maps Data or Program (CNF bit in Status Register ST1=0 Data, if it is ST1=1 Program
Memory R. Anil Kumar GRIET

37. Memory R. Anil Kumar GRIET
Memory maps
Program Memory:
Memory R. Anil Kumar GRIET

38. Memory R. Anil Kumar GRIET
Memory maps
Data Memory:
Memory R. Anil Kumar GRIET

39. Memory R. Anil Kumar GRIET
Memory maps: Data Memory
Memory R. Anil Kumar GRIET

40. Memory R. Anil Kumar GRIET
Memory maps
Input/output (I/O) space :
Memory R. Anil Kumar GRIET

41. Memory Addressing Modes
Immediate addressing mode
Direct addressing mode
Indirect addressing mode
Memory addressing mode R. Anil Kumar GRIET

42. Memory Addressing Modes
Immediate addressing mode:
Short immediate addressing: in this instruction will having an 8, 9, or bit constant as operand.
Ex: LACL #44h ; loads lower bits of accumulator with bits constant (44h in this case)
Note: for loading long 16-bit “LACC” command is used
Long immediate addressing: 16-bit constant is used that may be an absolute constant or as a 2’s complement value
Ex: LACC #4444h ; loads accumulator with 16-bit
Memory addressing mode R. Anil Kumar GRIET

43. Memory Addressing Modes
Direct addressing mode:
Data memory is first addressed in blocks of 128 words called Data Pages (DP)
Entire 64K of Data memory consist of 512 DP’s labeled 0 through 511
Current value determined by 9-bit DP pointer in status register ST0.
If DP is “ ”- current DP is 2
DP of particular memory address can be found by dividing hexadecimal address by 80h
Memory addressing mode R. Anil Kumar GRIET

44. Memory Addressing Modes
Direct addressing mode:
Memory addressing mode R. Anil Kumar GRIET

45. Memory Addressing Modes
Direct addressing mode:
In addition to DP, DSP must know particular word referred on that page, which is determined by 7-bit offset
The 7-bit offset are the LSB’s of memory address, on total making a 16-bit memory address
Memory addressing mode R. Anil Kumar GRIET

46. Memory Addressing Modes
Direct addressing mode:
The following steps are followed to use direct addressing
Set DP, load appropriate value i.e. from 0 to 511 or 0 to 1FF in Hexadecimal into DP using LDP command.
LDP #0E1h ; sets data page pointer to E1h
LDP #225 ; sets data page pointer to 225 i.e E1 in hexadecimal
Specify the offset. Ex: if we want ADD instr. To use value at second address of current DP you would write ADD 1h
If DP Points to 300h, then above instr. Will add contents of 301h to accumulator
Memory addressing mode R. Anil Kumar GRIET

47. Memory Addressing Modes
Indirect addressing mode:
It doesn’t depend on data pages as that is in direct addressing
In this type of addressing, you need to load memory space that is to be accessed into one of the auxiliary registers (ARx)
To select specific auxiliary register, load the 3-bit auxiliary register pointer (ARP) with a value from 0 to 7
ARP can be loaded with MAR or LARP
EX1: using MAR: ADD * , AR1 ;add using current *,then makes AR1 the new current AR for future use
Memory addressing mode R. Anil Kumar GRIET

48. Memory Addressing Modes
EX2: using LARP: LARP #2 ;this will make AR2 the current AR
Types of Indirect addressing mode:
No increment or decrement
Increment or decrement by 1:increments or decrements the content of the current auxiliary register by one
Increment or decrement by an index amount: increments or decrements the content of the current auxiliary register by the index amount.
Increment or decrement by an index amount using reverse carry
Memory addressing mode R. Anil Kumar GRIET

49. Memory Addressing Modes
Types of Indirect addressing mode:
Indirect addressing mode
Memory addressing mode R. Anil Kumar GRIET

50. Assembly programming using the C2xxDSP instruction set
Using assembly instruction set:
The following is the instruction syntax for the ADD command:
ADD dma [, shift] ; Direct addressing
ADD dma, 16 ; Direct with left shift of 16
ADD ind [, shift [, ARn]] ; Indirect addressing
ADD ind, 16 [, ARn] ; Indirect with left shift of 16
ADD #k ; Short immediate addressing
ADD #lk [, shift] ; Long immediate addressing
Assembly programming R. Anil Kumar GRIET

51. Assembly programming using the C2xxDSP instruction set
Using assembly instruction set:
Add the two numbers “2” and “3”:
LDP #6h ;loads the proper DP for dma 300h
SPLK #2, 300h ;store the number “2” in memory address 300h
LACL #3 ;load the accumulator with the number “3”
ADD 300h ;adds contents of 300h (“2”) to the contents
;of the accumulator(“3”); accumulator = 5
Assembly programming R. Anil Kumar GRIET