1. MAPLD 2005
Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM based FPGAs
Vikram Chandrasekhar, Sk. Noor Mahammad, V. Muralidharan
Dr. V. Kamakoti
Department of Computer Science and Engineering
Indian Institute of Technology Madras, India
Dr. N. Vijaykrishnan
Pennsylvania State University, U.S.A.

2. Outline of the talk Single Event Upsets (SEUs) in FPGAs Motivation
MAPLD 2005
Outline of the talk
Single Event Upsets (SEUs) in FPGAs
Motivation
Signal probability propagation for LUTs
Sensitivity of LUTs
Reduced Triple Modular Redundancy (RTMR)
SEU simulator
Experimental Results
Conclusions

3. Single Event Upsets (SEUs)
MAPLD 2005
Single Event Upsets (SEUs)
Circuit errors caused due to excess charge carriers induced primarily by external radiations
Cause an upset event but the circuit itself is not damaged

4. SEUs in LUTs Single Event Upset changes the function stored in LUT
MAPLD 2005
SEUs in LUTs
Single Event Upset changes the function stored in LUT
Behavior of the circuit configured on to the FPGA is modified

5. SEUs in a Switch Matrix Fault-free switch matrix Deletion of a net
MAPLD 2005
SEUs in a Switch Matrix
Fault-free switch matrix
Deletion of a net
Formation of a new net
Two nets are shorted

6. Motivation TMR hardened design takes 200% extra area
MAPLD 2005
Motivation
TMR hardened design takes 200% extra area
Certain logic blocks can halt the SEU propagation in the circuit
Focus is on the Boolean network of LUTs obtained after technology mapping
LUTs are more likely to stop SEUs rather than simple gates
Lesser redundancy in LUTs is required compared to redundant gates

7. Signal Probability Probability that a line carries a value ‘1’
MAPLD 2005
Signal Probability
Probability that a line carries a value ‘1’
Largely governed by the functions stored in the LUTs
Can be used to estimate the value carried by a line
The inputs are assigned random signal probabilities
Input values are propagated along Boolean network to the primary outputs
A threshold is fixed to get the expected value of a line from its signal probability

8. Signal Probability Propagation
MAPLD 2005
Signal Probability Propagation
Calculation of signal probability of an LUT’s output is dependent on the stored function
Signal probability of the LUT output is the probability of the input accessing a cell storing ‘1’
Can be computed as a sum of probability products similar to the sum-of-products form of the function
Let Mi  {0,1}, for 1  i  4, and
V = F(M1, M2, M3, M4)

9. Signal Probability Propagation
MAPLD 2005
Signal Probability Propagation
R(M1, P1) x R(M2, P2) x R(M3, P3) x R(M4, P4)
If V = 1
S (M1, M2, M3, M4) =
If V = 0
Where B
If A = 1
R (M1, M2, M3, M4) =
1 - B
If A = 0
The output signal probability is defined as
   
S (i, j, k, l )
i=0 j=0 k=0 l=0

10. Sensitive and Insensitive LUTs
MAPLD 2005
Sensitive and Insensitive LUTs
Input to an LUT can at most change by one bit - guideline for voter insertion
Sensitive LUT - a change in any one of the expected input values changes the output
Insensitive LUT - same value in all cells accessed due to a one-bit change in expected input
Insensitive LUTs stop the SEU effect from propagating any further
Form chains of sensitive LUTs that end at a voter followed by an insensitive LUT

11. MAPLD 2005
Insensitive LUTs

12. MAPLD 2005
Sensitive LUTs

13. Pseudo-insensitive LUTs
MAPLD 2005
Pseudo-insensitive LUTs
A sensitive LUT whose fanouts are all insensitive LUTs
An SEU effect passing through this LUT will not get past any of its fanouts
Such an LUT need not be triplicated
Cannot be treated as an insensitive LUT in identifying more pseudo-insensitive LUTs

14. Reduced Triple Modular Redundancy (RTMR)
MAPLD 2005
Assign random signal probabilities to primary inputs of the LUT network
Propagate the signal probabilities through the network till the primary outputs
Assign expected values to lines based on the threshold
Mark LUTs as either sensitive or insensitive
Find pseudo-insensitive LUTs and remark them
Triplicate every sensitive LUT identified in the circuit

15. RTMR For every sensitive LUT L Triplicate L
MAPLD 2005
RTMR
For every sensitive LUT L
Triplicate L
If all fanouts of L are sensitive LUTs
Connect the fanout of each copy of L to the corresponding copies of the fanout LUTs
Else
Connect the fanout of each copy of the LUT to the corresponding copies of the fanout sensitive LUTs
Insert a voter for the outputs of the three copies of the LUT
Connect the output of the voter to all the fanout insensitive and pseudo insensitive LUTs

16. SEU Simulation For given technology mapping circuit
MAPLD 2005
SEU Simulation
For given technology mapping circuit
A place and routing is performed using VPR tool
Net adjacencies are generated from the routing to simulate possible bridge faults
Using the technology mapping circuit, a Verilog model of the Boolean network is generated
The delays of the nets between the LUTs are extracted from the routing provided by the VPR tool

17. Net adjacencies generation
MAPLD 2005
SEU Simulator
Net adjacencies generation
Original Circuit
Faults
SEU Simulator
RTMR Circuit
simulate
simulate
Compare
Errors

18. MAPLD 2005
Fault generation
A random fault list is generated which consists errors like
Bridge Faults
Nets disconnections
Changes in the CLB SRAM cells

19. MAPLD 2005
Simulation
Each fault is simulated for a flexible duration of time to check the effectiveness of the RTMR circuit in tolerating the faults
Bridge faults are most important because errors are propagated through multiple paths in the network
Tougher to simulate since the RTMR circuit and the original circuit have different sets of possible SEU routing errors

20. MAPLD 2005
Experimental Results
Implemented on MCNC benchmark circuits to determine the required redundancy
Threshold for signal probability was varied between with nearly similar results
Berkeley Logic Interchange Format (BLIF) files of the circuits are used for RTMR

21. Area overheads of RTMR vs. TMR
MAPLD 2005
Area overheads of RTMR vs. TMR
4200
2766
48.79
1400
Tseng
11595
4544
8.78
3865
spla
5733
2535
16.33
1911
seq
16059
5947
5.55
5353
pdc
4431
2013
18.15
1477
misex3
17559
9166
28.3
5853
frisc
3486
1986
35.46
1162
ex5p
12543
5475
15.48
4181
elliptic
5625
2999
29.98
1875
diffeq
6465
3715
36.2
2155
des
39480
16326
12.03
13160
clma
3864
1648
13.98
1288
apex4
No. of LUTs in TMR circuit
No. of LUTs in RTMR circuit
Percentage of sensitive LUTs
No. of LUTs in original circuit
Benchmark Circuit

22. Conclusion and future work
MAPLD 2005
Conclusion and future work
On an average, only 38% additional redundancy is required
Insignificant loss of SEU immunity is observed using the SEU simulator
Further study of the tradeoff between SEU immunity and LUT redundancy is required