1. ‘if-else’ & ‘case’ Statements
Additional notes:
Source: Slides from ‘The Verilog HDL’, Prof. Don Thomas, Carnegie Mellon University (CMU)

2. 4 EMT 351/4 DIGITAL IC DESIGN Verilog Behavioural Modeling (Part 2)
Week #
Verilog Behavioural Modeling
(Part 2) 4

3. Contents Procedural Assignments Verilog Behaviors
Continuous assignment (‘assign’)
Single-pass behaviour (initial)
Cyclic behaviour (‘always’)
Procedural Assignments
Blocking assignments
Non-blocking assignments
Procedural continuous assignments (next lecture)

4. Behavioural Modeling In last lecture, we learnt that..
There are 3 types of behavioral models:
Continuous assignments (‘assign’)
Single-pass behaviours (‘initial’)
Cylic behaviours (‘always’)
.. Today, we will learn about the details for each behaviour..

5. Continuous Assignment
A counterpart of Boolean equations that describe combinational logic
Format:
A module may include multiple continuous assignment, all active concurrently with each other
assign net_variable = expression
Commonly used net type:
wire
Boolean equation,
conditional operator

6. Single-Pass Behavior (‘initial’)
Keyword: initial
One-shot activity flow and expires after all procedural statements have completed execution
Typically use to initialize a simulation and create stimulus waveforms for testbench
Forms of initial block:
Individual statement (terminated by ;)
A ‘begin … end’ block
A ‘fork … join’ block

7. Single-Pass Behavior (‘initial’)
initial // individual statement
A = 0;
initial // with begin .. end
begin // statements executed sequentially
reset = 0;
#10 reset = 1;
#5 reset = 0;
end
initial // with fork .. join
fork // statements executed concurrently
#5 B <= ~A;
#10 C <= A;
join
reset 5 10 15 20 25
Example B C 5 10 15 20 25

8. Cyclic Behaviour (‘always’)
Keyword: always
Cyclic activity flow whereby the procedural statements will be re-execute after the last procedural statement has executed
Re-execution process continues indefinitely until the simulation is terminated
They execute procedural statements to generate values of the variable, manipulate, & store the variables in memory

9. Cyclic Behaviour (‘always’)
The statements in cyclic behaviour can be unconditional or controlled by a sensitivity list
Used to model (& synthesize) level-sensitive & edge-sensitive behaviour
level-sensitive  combinational logic
edge-sensitive  sequential logic
posedge (sensitive to +ve edge of signal)
negedge (sensitive to –ve edge of signal)

10. Cyclic Behaviour (‘always’)
Example: 2-input full adder
module full_adder (sum, c_out, a, b, c_in);
input a, b, c_in;
output sum, c_out;
(a or b or c_in)
begin
sum = a ^ b ^ c_in;
c_out = (a & b) | (b & c_in) | (a & c_in);
end
endmodule
sensitivity list
- level-sensitive
block
statement
QUESTION:
How to synchronize this module to a clock signal? Rewrite the module so that the design is sensitive to positive edge of clock.
ANSWER:
Include clock as input signal, & sensitivity list (posedge clock)

11. Single-Pass vs Cyclic initial begin … imperative statements .. end
Runs when simulation starts
Terminates when control reaches the end (execute once & stop)
Good for providing stimulus for testbench
Not use in synthesis
always
begin
… imperative statements ..
end
Runs when simulation starts
Restarts when control reaches the end (continually loop)
Good for modeling / specifying hardware
Use in synthesis

12. Combination of Single-Pass & Cyclic
module clock_gen (clock);
parameter half_cycle = 50;
parameter max_time = 1000;
output clock;
reg clock;
initial
clock = 0;
always
begin
#half_cycle clock = ~clock;
end
#max_time $finish;
endmodule
unconditional ‘always’ block (without sensitivity list)
NOTE:
Usually used in testbench

13. Procedural Assignment
Statement that assigns value to a register variable (i.e. to data objects of type reg, integer, real, realtime, time)
The output only can get value when a procedural statement executes

14. Procedural Assignment
3 types of procedural assignments
Use “=” operator
BLOCKING ASSIGNMENT
Use “<=” operator
NON-BLOCKING ASSIGNMENT
Use keywords ‘assign … deassign’, ‘force … release’
PROCEDURAL CONTINUOUS ASSIGNMENT (PCA)

15. Blocking Assignment The blocking assignments operator is “=”
Blocking assignments must evaluate the right-hand-side (RHS) arguments w/o interruption from any other Verilog statements
The assignment is said to "block" other assignments until the current assignment has completed

16. Blocking Assignment
Execution of blocking assignments can be viewed as a one-step process:
“Evaluate the RHS and update the LHS of the blocking assignment without interruption from any other Verilog statement.”

17. Blocking Assignment
If blocking assignments are not properly ordered, a race condition can occur
When blocking assignments are scheduled to execute in the same time step, the order execution is unknown

18. Blocking Assignments Simulation example always @ (posedge clk) a = b;
b = a;
// 2 concurrent ‘always’ block with blocking statements
either (a = b) or (b = a) will be executed first, depend to the simulator implementation
so, values in register a and b will not be swapped  both of the register (a and b) will get the same value
Simulation example
clk a b 5 10 15 20 25
For this example, which ‘always’ block execute first?

19. Non-blocking Assignment
Non-blocking assignment operator is the same as the less-than-or-equal-to operator ("<=").
A non-blocking assignment must evaluates the RHS expression at the beginning of a time step and schedules the LHS update to take place at the end of the time step

20. Non-blocking Assignment
The non-blocking assignments executes concurrently (in parallel) regardless to the sequence appearance in a block statement
Variables from RHS are sampled, held in memory, & used to update the LHS variable concurrently

21. Non-blocking Assignment
The non-blocking assignment does not block other Verilog statements from being evaluated
Execution of non-blocking assignments can be viewed as a two-step process:
Evaluate the RHS of non-blocking statements at the beginning of the time step
Update the LHS of non-blocking statements at the end of the time step

22. Non-blocking Assignment
REMEMBER!
Non-blocking assignments are only made to register data types and are therefore only permitted inside of procedural blocks, such as initial blocks and always blocks
Non-blocking assignments are not permitted in continuous assignments (‘assign’)

23. Non-blocking Assignments
(posedge clk)
a <= b;
b <= a;
// 2 concurrent ‘always’ block with non- blocking statements
at +ve edge clock, the values of all RHS variables are ‘read’ & the RHS expressions are evaluated & stored in temporary variables
during ‘write’ operation, the values stored in temporary variables are assigned to LHS variables  values are swapped correctly, regardless of the order in which the write operation are performed
Simulation example
clk a b 5 10 15 20 25

24. Concentrate on condition
Additional Notes
READ YOURSELF!!
Example: Feedback oscillator with blocking assignments
module fbosc1 (y1, y2, clk, rst);
output y1, y2;
input clk, rst;
reg y1, y2;
(posedge clk or posedge rst)
if (rst) y1 = 0; // reset
else y1 = y2;
if (rst) y2 = 1; // preset
else y2 = y1;
endmodule
Concentrate on condition
rst == 0

25. Additional Notes Simulation of fbosc1 @ posedge clk or reset = 1
 y1 = 0, y2 = 1
Unknown condition here coz no initial value of y1 & y2
@ posedge clk and reset = 0
y1 = 1, y2 = 1
(race condition – which ‘always’ block execute first?)
Simulation of fbosc1

26. Additional Notes
According to the IEEE Verilog Standard, the two always blocks can be scheduled in any order
If the first always block executes first after a reset, both y1 and y2 will take on the value of 1
If the second always block executes first after a reset, both y1 and y2 will take on the value 0
This clearly represents a Verilog race condition

27. Concentrate on condition
Additional Notes
Example: Feedback oscillator with non-blocking assignments
module fbosc2 (y1, y2, clk, rst);
output y1, y2;
input clk, rst;
reg y1, y2;
(posedge clk or posedge rst)
if (rst) y1 <= 0; // reset
else y1 <= y2;
if (rst) y2 <= 1; // preset
else y2 <= y1;
endmodule
AGAIN..
Concentrate on condition
rst == 0

28. Additional Notes Simulation of fbosc2 @ posedge clk or reset = 1
 y1 = 0, y2 = 1
@ posedge clk and reset = 0
y1 = 0, y2 = 1
(new value of y1 & y2 of takes the value at the beginning of the time step (previous cycle)
Unknown condition here coz no initial value of y1 & y2
@ posedge clk and reset = 0
y1 = 1, y2 = 0
(new value of y1 & y2 of takes the value at the beginning of the time step (previous cycle)
Simulation of fbosc2

29. Verilog Coding Guidelines
Adherence to these guidelines will help to remove % of the Verilog race conditions encountered by most Verilog designers
When modeling sequential logic, use non-blocking assignments
When modeling latches, use non-blocking assignments
READ YOURSELF!!

30. Cont..
When modeling combinational logic with an ‘always’ block, use blocking assignments
When modeling both sequential and combinational logic within the same always block, use non-blocking assignments
Do not mix blocking and non-blocking assignments in the same ‘always’ block
READ YOURSELF!!

31. Cont..
Do not make assignments to the same variable from more than one ‘always’ block
Use $strobe to display values that have been assigned using non-blocking assignments
Do not make assignments using #0 delays
READ YOURSELF!!