1. Andrew Putnam University of Washington RAMP Retreat January 17, 2008
RAMP Infrastructure
Andrew Putnam
University of Washington
RAMP Retreat
January 17, 2008

2. Complaint
I can’t get RAMP [color] to work because Greg doesn’t have [feature] in RDLC.

3. Fundamental Problem RDLC will someday support: But what do we do now?
Platform independence
Tool independence
Integrated debugging
HW / SW integration
But what do we do now?
Use existing tools? (EDK, Synplicity, BlueSpec…)
How do we make sure it’s compatible with RDL?

4. Problem Statement RDLC3 is a tool in development
We need a way to make progress when RDLC is missing features
Solution: provide a clear, simple coding specification for hand-coded modules (RDF)
Ensure that these are compatible with RDL

5. Terminology – Inside the Riddle
RDF: RAMP Design Framework
RDL: RAMP Design Language
RDLC: RAMP Design Language Compiler
RDLC
RDL
RDF

6. RDF Model

7. RDF Model (Detailed)
See Greg’s Breakout Presentation for more details

8. FSL Unit/Channel FSL Link __WRITE __READ FSL Control __VALID __VALID
__READY
__READY
__STALL
__STALL
Data
Control
Write
Full
Data
Control
Read
Exists
FSL
Output
FSL
Input
Implementation varies based on Latency, Bitwidth, FIFO Depth

9. Andrew Putnam University of Washington RAMP Retreat January 17, 2008
RAMP Purple
Andrew Putnam
University of Washington
RAMP Retreat
January 17, 2008

10. Simple, Correct >> Fast, Buggy
Eric Chung (CMU)
Jan 08 RAMP Retreat

11. Basic Idea Use the RAMP library of parts when you can
Use MicroBlaze to prototype parts you don’t have
Refine the MicroBlaze to HDL
Add your HDL to the RAMP library

12. Baseline RAMP Systems System Proc. to Proc. Communication Processor
O/S per core
#cores / FPGA (BEE2)
RAMP Red
Transactional Memory
PowerPC
Linux 2
RAMP Blue
Message Passing
MicroBlaze v4.0
ucLinux
8-12
RAMP White
Coherent Shared Memory
PowerPC / LEON

13. Baseline RAMP Systems System Proc. to Proc. Communication Processor
O/S per core
#cores / FPGA (BEE2)
RAMP Red
Transactional Memory
PowerPC
Linux 2
RAMP Blue
Message Passing
MicroBlaze v4.0
ucLinux
8-12
RAMP Purple
Coherent Shared Memory
MicroBlaze v6.0
Xilinx MicroKernel
RAMP White
PowerPC / LEON

14. Proc
Proc
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15. Proc
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16. Proc
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Proc D$ D$ D$ D$
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17. L3 L3 L3 L3 Proc Proc Proc Proc Proc Proc Proc Proc D$ D$ D$ D$ ProcI$
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Proc L3 L3
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18. RAMP Purple Compute Node
Cycle Control
FSL Input Control
Processor
(MicroBlaze)
Clk
Clk
FSL Output Control

19. RAMP Purple Compute Node
Reuse commercial IP if it can be clock gated
Can’t have internal clock management
Can’t have negative-edge sensitivity
~8-16 BUFGMUXs / FPGA, which limits cores / chip
Processor
(MicroBlaze)
Cycle Control
Clk
FSL Output Control
FSL Input Control

20. RAMP Purple Cache Processor (MicroBlaze) Cycle Control Start Done
FSL Input Control
Processor
(MicroBlaze)
Clk
Clk
FSL Output Control
DRAM Port (non-RDF)

21. RAMP Purple Cache MicroBlaze emulation of generic unit
Monitor special memory locations for Start, Done
Sure it’s slow
250 MHz on Virtex-5
Processor
(MicroBlaze)
Cycle Control
Clk
FSL Output Control
FSL Input Control
Start
Done
DRAM Port (non-RDF)

22. FSL Unit/Channel FSL Link __WRITE __READ FSL Control __VALID __VALID
__READY
__READY
__STALL
__STALL
Data
Control
Write
Full
Data
Control
Read
Exists
FSL
Output
FSL
Input
Implementation varies based on Latency, Bitwidth, FIFO Depth

23. Software Control Core -- Linux Compute Cores -- Xilinx MicroKernel
Handles syscalls
Dispatches jobs to compute cores
Could be arranged hierarchically
Compute Cores -- Xilinx MicroKernel
XMK provides libc, p-thread, scheduling, semaphores
Cores wait on task queue in main memory
Floating point unit is optional, can be shared

24. RAMP Purple  WaveScalar
Processor
Processor
Processor
Processor
Coherent Data Cache
Instruction Cache
Processor
Processor
Processor
Processor

25. RAMP Purple  WaveScalarPE PE PE PE
Coherent Data Cache
Instruction Cache PE PE PE PE

26. RAMP Purple  WaveScalarPE PE PE PE
Coherent Data Cache I$ I$ I$ I$ PE PE I$ I$ I$ I$ PE PE

27. RAMP Purple  WaveScalarPE I$ PE I$ PE I$ PE I$
WaveOrdered Coherent Data Cache PE I$ PE I$ PE I$ PE I$

28. RAMP Purple  WaveScalarPE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$
WaveOrdered Coherent Data Cache PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$

29. WaveOrdered Coherent Data Cache
WaveScalar Cluster PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$
WaveOrdered Coherent Data Cache PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$ PE I$

30. You were meant for me. Perhaps as a punishment.
Destiny:
You were meant for me. Perhaps as a punishment.