1. CMOS Process Flow

2. 1- Wafer Selection and Cleaning

3. 2- Active Region Formation LOCOS Process3 2 1 4 5 6

4. 2- Active Region Formation LOCOS Process7 8 9

5. 3- N and P Well Formation 1 2 3
Done in 2 ways 4

6. 4- Vth Adjustment (Field Implant)1 2 3

7. Removal of Gate Oxide Layer
5- Polysilicon Formation (Gate) 3 1 2
Removal of Gate Oxide Layer
Gate Oxide Re-growth
Deposition of Polysilicon Electrode 4
Polysilicon Etching
Why did we leave the SiO2 from the beginning?
To avoid channeling
The SiO2 atoms are amorphous so the ions are randomized and stop when they hit an atom.
The P- type silicon is single crystalline.

8. 6- Lightly Doped Drain
N+ N- P instead of N+ P to avoid high electric field between N+ and P 1 2
Self Alignment
The polysilicon gate is used to align the drain and source without using a mask

9. Formation of Sidewall Spacer1 2 3
Deposition of “Screen” Oxide Layer

10. 7- Formation of Source and Drain1 2

11. 8- Annealing (Drive in Process)
Very high temperature then cooling to relax the bonds in the material 1 2

12. 9- Metal Interconnect 1 2 3 5 6 4 Ti N2
Titanium and N+ form titanium-silica which is a very good conductor
Titanium and Nitrogen form titanium-nitride which is also a conductor 1 2 3 Ti N2 5 6 4
Planarization by Chemical Mechanical Polishing (CMP)

13. 9- Metal Interconnect 8 7 Open holes for via
Why is the annealing done before the metal interconnect?
Because the metal will melt

15. 1 2 3 4 A heavily doped P substrate is chosen
A lightly doped layer is grown on top
Active Region Formation (LOCOS) and P implant 3 4
N well Formation
High Temperature to complete N well Formation

16. 5 6 7 8 Vth Adjustment (Field Implant) Vth Adjustment (Field Implant)
Polysilicon Deposition

17. 10 9 11 Gates Source and Drain Formation (Self Alignment)