1. University of California Los Angeles
Status of the ALCT
Martin von der Mey
University of California Los Angeles
Effects of SEUs
ALCT2001 status
Old radiation test results
New results
SEU handling
Conclusion

2. ALCT Status
ALCT is the CSC anode trigger and readout board (Anode Local Charged Track)
ALCT2000 prototype worked but…
FPGAs suffered frequent “upsets” (program changes) with neutron radiation
Reload of FPGAs took “long” 150ms
Changed from Altera FPGAs to Xilinx for ALCT2001
With Xilinx reload of FPGA takes 40 ms
On-chamber electronics needs to be delivered well before installation
Therefore, ALCT schedule is now a critical path item for Emu.
ALCT2001 being tested and in good shape.
ALCT2001 was tested at UC Davis.

3. ALCT Functions
Inputs discriminated signals from AFEB front-end boards, provides AFEB support:
Distributes power and shut-down signals.
Sets and reads back discriminator thresholds.
Creates and distributes amplifier/discriminator test pulses.
Delay/translator ASIC on input does time alignment with bunch crossings.
Searches for muon patterns in anode signals. If found, sends information to Trigger Motherboard.
Records input and output signals at 40 MHz (up to 672 channels/board) in case of Level 1 trigger.
Other support functions:
Creates and distributes test pulses for test strips.
Controls delay ASICs with 2ns precision (0-30 ns setting).
Reads board currents, voltages, and temperature.

4. ALCT2001 Modifications Radiation-related Design improvements
Hardware change from Altera to Xilinx FPGAs – loads faster. Needed firmware change from AHDL to Verilog. (Alex)
Hard reset signal from TMB starts reload of FPGAs from rad-hard EEPROMs.
Design improvements
Replace multiple Ball-Grid Arrays (BGA) by single chip on mezzanine card.
XCV600E and 1000E (identical packages). In moment we use XCV1000E.
Under investigation the use of Virtex II.
40-to-80 MHz multiplexors required for single-chip design.
4 JTAG chains. Chains are independent.
Robustness, testing
Very stiff mezzanine card holding ball-grid array.
Delay chips now allow pattern loading in order to test critical input ball grid array connections. Bad connections found loading patterns into the Delay chips and reading back the Virtex FIFO.

5. Power, computer connectors
New ALCT Boards
Power, computer connectors
80 MHz SCSI outputs
(to Trigger Motherboard)
Xilinx mezzanine card
Main board for 384-ch type
Delay/ buffer ASICs,
2:1 bus multiplexors (other side)
Input signal connectors
Analog section:
test pulse generator, AFEB power,
ADCs, DACs
(other side)

6. ALCT-672 Version (also -288)

7. Present Status
Prototype batch of 6 ALCT boards and mezzanine boards produced and tested
Debugging of these boards is ongoing
Smoke tests passed on all 6 ALCT board.
Test program written and tested.
Slow Control functions are now fully debugged.
Virtex FPGAs successfully downloaded and project is “alive”, registers can be written and read back. Patterns and delays written to Delay ASICs and verified reading out FIFO in Virtex FPGA.
TMB functions have to be implemented.
Download project using Linux box.
Layout: ALCT-672 is complete, ALCT-288 is ongoing. Probably finished next week.

8. Hardware
The TMB functions have still to be included into the firmware.
Known simple design mods required/desired:
Adopt known rad-tolerant regulator for test pulse circuit.
Move a couple of jumpers and test points out from under mezzanine card.
Change 8-bit ADCs to 10-bit.
Change maximum threshold from 2.5 V to 1.2 V.
ALCT2001 ready for production.

9. Software
Linux control software developed for Virtex FPGA and Slow Control chip.
Porting Alex windows software to Linux. Writing and reading Delay lines
Implementing download routines for Virtex FPGA and Slow Control chip from Linux.
Write test program for the ALCT2001 testing board.

10. Some Test Results Thresholds: Virtex loading time (38ms).
(ADC-DAC) +2*Channel vs. DAC setting.
Essentially perfect behavior
Virtex loading time (38ms).
Virtex power about 1 watt.

11. Effect of an ALCT SEU Is a random effect
Uncorrelated between muon stations
Doesn’t affect CLCT or cathode data
A chamber is not “dead”
An inefficiency for the trigger
Is mainly an issue for ME1/1 trigger efficiency
Other stations: rates down by 4 or much more
Puts ALCT2001 into an unknown state
Makes reload of project into FPGA necessary
All on-chamber electronics should survive the worst-case radiation environment (ME1/1)
Neutron Fluence (>100 keV): 6.2 x 1011 cm-2 .
Total Ionizing Dose: 1.8 kRad.

12. New results Radiation tests at UC Davis…
Cyclotron with proton beam (63.3 MeV)

13. SEU Measurements Any bit errors during self-test Calculations:
SEU s = ( )*10-9 cm2 per chip
L = 4*104/cm2/s flux estimate ME1/1 x3
SEU s*L = 9.2*10-5/s rate per chip x3
SEU s*L = 3.7*10-4/s rate per board (4 chips) x3
Note - SEUs are better than deadtime:
SEUs are uncorrelated between muon stations
Muons still leave cathode LCTs for both trigger & DAQ
Dead time is incurred for all of CMS if synch’ed
Any bit errors during self-test

14. New Refresh Calc’s Non-redundant logic: Triple-redundant logic:
s *L= 9*10-5/s rate per board (4 chips) x3
refresh every 80 sec
0.15s/80s = 0.19% refresh dead time
0.5% SEU-affected boards in ME1/1
<0.125% SEU in other stations
Triple-redundant logic:
s *L= 1.2*10-5/s rate per board (4 chips) x3
refresh every 200 sec
0.15s/200s = 0.07% refresh dead time
0.24% SEU-affected boards in ME1/1
<0.06% SEU in other stations
Without x3 rate safety factor, it’s about 600s between refresh, and 0.02% dead time

15. Virtex FPGA
Loop over 64 WG, inject patterns into Delay chips and read out FIFO of Virtex FPGA (Alex).
Irradiate Virtex FPGA with
50 pA beam current
100 pA beam current
10 pA beam current
Radiation results shows small improvements to before…
SEU at 60.6 Rad compared to 59.2 Rad before…
The main improvement comes due to combination of 5 chips (1 concentrator and 4 LCT chips into 1).

16. Virtex FPGA Calculations : 0.65% SEU-affected boards in ME1/1
SEU s = 2.1*10-9 cm2
L = 1.3*104/cm2/s flux estimate ME1/1
SEU s*L = 2.7*10-5/s rate per board
Refresh every 240 s (4 min.)
0.04s/240s = % dead time
0.65% SEU-affected boards in ME1/1
<0.15 % in other stations

17. Virtex FPGA Check configuration of FPGA using Xilinx Verify function
Expose Virtex FPGA to 10 pA protons:
5 sec (0.001 kRad) : no errors
10 sec (0.002 kRad) : 5 errors
20 sec (0.005 kRad) : 3 error
120 sec (0.031 kRad) : Too many errors for reading back
SEU s = 1.73 x 10–7 cm2 . (Much higher)
Result :
Many configuration errors. But they do not influence final results.

18. Virtex EPROM Move board to irradiate EPROM
After radiation verify logic in EPROM using
Xilinx Foundation
Radiated EPROM for 5 minutes at
100 pA (0.70 kRad)
500 pA (3.48 kRad)
1000 pA (7.04 kRad)
Checked logic using Xilinx Foundation
Result :
No errors were found
No problem for LHC

19. Bus multiplexor Irradiated bus multiplexors with 1nA for 5 minutes
14.47 kRad beam current (14.47 kRad)
kRad beam current (7.05 kRad)
Used Alex program to write and read patterns into
delay lines and read back FIFO in Virtex FPGA.
Results :
No errors found

20. Delay ASICs Move to Delay ASICs Irradiate 4 ASICs with 1 nA beam
While irradiation write and read delay Lines and read back FIFO.
After 20.3 kRad no error found
Results :
As expected no problems with the Delay ASICs
are expected for CMS.

21. Slow Control FPGA Irradiate Slow Control FPGA with…
50 pA proton beam current
100 pA beam current
500 pA beam current
Flat distribution with mean at
293.3 Rad
No problem to expect for
Spartan XL FPGA
Calculations :
SEU s = 0.5*10-9 cm2
L = 1.3*104/cm2/s flux estimate ME1/1
SEU s*L = 0.7*10-5/s rate per board
If refresh every 240 s (4 min.)
0.04s/240s = % dead time
0.16% SEU-affected boards in ME1/1

22. ADC/DAC Test No errors but damaged ADCs/DACs.
Irradiate ADCs and DACs with
100 pA and total of kRad (DACs)
500 pA and total of kRad (DACs)
500 pA and total of kRad (ADCs)
Results :
No errors but damaged ADCs/DACs.
No problems to expect for CMS.

23. Conclusions A lot of work done:
Improvements in Hardware, Software and Firmware.
Debugging of Virtex FPGA and Slow Control FPGA went well.
New software developed. Helpful for fastsites later.
Xilinx loads faster:
40ms vs. 150ms
Now Virtex chip includes functions of 5 previous ones.
Radiation test shows that the most of the electronic components of the ALCT2001 are radiation safe.
A refresh every 4min is necessary to minimize SEU.
ALCT2001 is in good shape and ready for production.