1. Upgrade of the CSC Endcap Muon Port Card and Optical Links to CSCTF
7/2/2018
Upgrade of the CSC Endcap Muon Port Card and Optical Links to CSCTF
Mikhail Matveev
Rice University
31 October 2012

2. MPC Upgrade Requirements
7/2/2018
MPC Upgrade Requirements
■ Be able to deliver all 18 trigger primitives from the EMU peripheral
crate to the upgraded Sector Processor
■ Preserve sorting capabilities of the Muon Port Card
■ Preserve 3 old 1.6Gbps optical links to the existing CSCTF

3. Upgrade Developments Use existing Muon Port Card main board
7/2/2018
Upgrade Developments
Use existing Muon Port Card main board
- TMB interface remains unchanged (2 LCTs per 80MHz)
- 3 “old” optical links are still available
Original design was based on Xilinx Virtex-E XCV600E FPGA
New prototype (2012) is based on Xilinx Spartan-6 FPGA
- Inexpensive FPGA ($280 for
the fastest speed grade chip)
- 8 embedded GTP serializers
- 3.2Gbps/channel data rate
- Modest power consumption
- SNAP12 optical transmitter

4. Spartan-6 Mezzanine new old
7/2/2018
Spartan-6 Mezzanine
First prototype was built and successfully tested with the Sector Processor prototype SP10 in April 2012
- SP10 receivers are based
on Virtex-6 GTX blocks
- Optical PRBS test: BER<10-13
- Various other tests and
measurements (next slides)
Second prototype built in October
- Few schematic fixes
- More reliable connector to
attach the SNAP12 board
new
old

5. 7/2/2018
New Mezzanine

6. Old and New Mezzanines Installed
7/2/2018
Old and New Mezzanines Installed

7. SERDES Latency ■ Present MPC-to-SP system at CMS:
7/2/2018
SERDES Latency
■ Present MPC-to-SP system at CMS:
- TLK2501 Transmitter (1.6Gbps - 80MHz)
~23 ns
- TLK2501 Receiver (1.6Gbps - 80MHz)
~57 ns
■ New system (prototypes):
- Spartan-6 GTP Transmitter (3.2Gbps – 160MHz)
~20 ns (without Tx buffer)
- Virtex-6 GTX receiver (3.2Gbps – 160MHz)
~69 ns (without Rx buffer)

8. 7/2/2018
Other Measurements
■ Successful test with 9 Trigger Motherboards in the peripheral crate
■ Three old 1.6Gbps links have been verified
■ Power consumption:
- Spartan-6 FPGA
~1A Vccint (1.2V)
~0.15A Vccaux+Vcco (3.3V)
~ 0.8A GTPs (1.2V)
- Three MIC69501 voltage regulators on a mezzanine board
passed irradiation test at TAMU in 2011
- MPC (main board + Spartan-6 mezzanine)
3.3V

9. Production Cost Estimate
7/2/2018
Production Cost Estimate
Cost
Spartan-6 FPGA
$280
Optical Transmitter
$600
Other components
$300
Fabrication and Assembly, mezzanine
$400
Fabrication and Assembly, optical transmitter
$80
Total
$1,660
● Will need 80 mezzanines ($132,800)

10. Optical Fibers: 2 Options
7/2/2018
Optical Fibers: 2 Options
(1) Trunk cable with 4 or 8 connectorized cords (similar to one proposed for the DT upgrade). Each cord has 12 fibers. Will need 36 cables for 60 peripheral crates, one spare cord per crate.
(2) New single fibers blown inside the spare conduits of the existing installation. 144 patch cords with MPO connectors.
discussion with the CERN Electrical Engineering group is underway;
expect to converge by the end of 2012

11. 7/2/2018
MPC Upgrade Plans
■ Proceed with the Spartan-6 pre-production prototype design
- equip 3 Muon Port Cards with new mezzanines and test by
December 2012
- integration tests with the uTCA SP board: January-May 2013
- irradiation test: spring 2013
- proceed with another prototype if needed: June-August 2013
■ Production, Installation and Commissioning
- buy parts, fabricate PCBs: 1 November 2013 – 31 December 2013
- assemble 80 mezzanine boards: 1-31 January 2014
- tests boards at Rice (1 board/day): 1 February – 30 April 2014
- ship to CERN: May 2014
- install at CMS: 1 June – 31 July 2014
- commissioning with the peripheral electronics and TF:
1 August – 30 October 2014